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23091659f3
Currently the assembler would accept, e.g. `ldr r0, [s0, #12]` and similar. This patch add checks that only general-purpose registers are used in address operands, shifted registers, and shift amounts. Differential revision: https://reviews.llvm.org/D39910 llvm-svn: 321866
51 lines
1.9 KiB
ArmAsm
51 lines
1.9 KiB
ArmAsm
@ RUN: not llvm-mc -triple=armv7a-eabi < %s 2>&1 | FileCheck %s
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ldr r4, [s1, #12]
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@ CHECK: [[@LINE-1]]{{.*}}error: invalid operand for instruction
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ldr r4, [d2, #12]
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@ CHECK: [[@LINE-1]]{{.*}}error: invalid operand for instruction
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ldr r4, [q3, #12]
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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ldr r4, [cpsr, #12]
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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ldr r4, [r1, s12]
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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ldr r4, [r1, d12]
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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ldr r4, [r1, q12]
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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ldr r4, [r1, cpsr]
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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ldr r4, [r3], s12
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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ldr r4, [r3], d12
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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ldr r4, [r3], q12
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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ldr r4, [r3], cpsr
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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add r3, r0, s1, lsl #2
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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add r3, r0, d1, lsl #2
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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add r3, r0, q1, lsl #2
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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add r3, r0, cpsr, lsl #2
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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add r3, r0, r1, lsl s6
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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add r3, r0, r1, lsl d6
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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add r3, r0, r1, lsl q6
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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add r3, r0, r1, lsl cpsr
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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ldrd r2, r3, [s4]
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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ldrd r2, r3, [r4, s5]
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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ldrd r2, r3, [r4], s5
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@ CHECK: [[@LINE-1]]{{.*}} invalid operand for instruction
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