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a1d7f2fdc1
Those two subtarget features were awkward because their semantics are reversed: each one indicates the _lack_ of support for something in the architecture, rather than the presence. As a consequence, you don't get the behavior you want if you combine two sets of feature bits. Each SubtargetFeature for an FP architecture version now comes in four versions, one for each combination of those options. So you can still say (for example) '+vfp2' in a feature string and it will mean what it's always meant, but there's a new string '+vfp2d16sp' meaning the version without those extra options. A lot of this change is just mechanically replacing positive checks for the old features with negative checks for the new ones. But one more interesting change is that I've rearranged getFPUFeatures() so that the main FPU feature is appended to the output list *before* rather than after the features derived from the Restriction field, so that -fp64 and -d32 can override defaults added by the main feature. Reviewers: dmgreen, samparker, SjoerdMeijer Subscribers: srhines, javed.absar, eraman, kristof.beyls, hiraditya, zzheng, Petar.Avramovic, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D60691 llvm-svn: 361845
45 lines
2.2 KiB
ArmAsm
45 lines
2.2 KiB
ArmAsm
@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-D32
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@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null -mattr=-d32 %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-D16
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// First operand must be a GPR
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vldm s0, {s1, s2}
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// CHECK: error: operand must be a register in range [r0, r15]
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// CHECK-NEXT: vldm s0, {s1, s2}
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vstm s0, {s1, s2}
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// CHECK: error: operand must be a register in range [r0, r15]
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// CHECK-NEXT: vstm s0, {s1, s2}
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// Second operand must be a list of SPRs or DPRs
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vldm r0, {r1, r2}
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// CHECK: error: invalid instruction, any one of the following would fix this:
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// CHECK-NEXT: vldm r0, {r1, r2}
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// CHECK: note: operand must be a list of registers in range [s0, s31]
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// CHECK-D32: note: operand must be a list of registers in range [d0, d31]
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// CHECK-D16: note: operand must be a list of registers in range [d0, d15]
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vldm r0, #42
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// CHECK: error: invalid instruction, any one of the following would fix this:
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// CHECK-NEXT: vldm r0, #42
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// CHECK: note: operand must be a list of registers in range [s0, s31]
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// CHECK-D32: note: operand must be a list of registers in range [d0, d31]
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// CHECK-D16: note: operand must be a list of registers in range [d0, d15]
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vldm r0, {s1, d2}
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// CHECK: error: invalid register in register list
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// CHECK-NEXT: vldm r0, {s1, d2}
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vstm r0, {r1, r2}
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// CHECK: error: invalid instruction, any one of the following would fix this:
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// CHECK-NEXT: vstm r0, {r1, r2}
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// CHECK: note: operand must be a list of registers in range [s0, s31]
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// CHECK-D32: note: operand must be a list of registers in range [d0, d31]
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// CHECK-D16: note: operand must be a list of registers in range [d0, d15]
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vstm r0, #42
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// CHECK: error: invalid instruction, any one of the following would fix this:
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// CHECK-NEXT: vstm r0, #42
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// CHECK: note: operand must be a list of registers in range [s0, s31]
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// CHECK-D32: note: operand must be a list of registers in range [d0, d31]
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// CHECK-D16: note: operand must be a list of registers in range [d0, d15]
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vstm r0, {s1, d2}
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// CHECK: error: invalid register in register list
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// CHECK-NEXT: vstm r0, {s1, d2}
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