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51463c570e
This patch adds support for recognizing more patterns to match to DEXT and
CINS instructions.
It finds cases where multiple instructions could be replaced with a single
DEXT or CINS instruction.
For example, for the following:
define i64 @dext_and32(i64 zeroext %a) {
entry:
%and = and i64 %a, 4294967295
ret i64 %and
}
instead of generating:
0000000000000088 <dext_and32>:
88: 64010001 daddiu at,zero,1
8c: 0001083c dsll32 at,at,0x0
90: 6421ffff daddiu at,at,-1
94: 03e00008 jr ra
98: 00811024 and v0,a0,at
9c: 00000000 nop
the following gets generated:
0000000000000068 <dext_and32>:
68: 03e00008 jr ra
6c: 7c82f803 dext v0,a0,0x0,0x20
Cases that are covered:
DEXT:
1. and $src, mask where mask > 0xffff
2. zext $src zero extend from i32 to i64
CINS:
1. and (shl $src, pos), mask
2. shl (and $src, mask), pos
3. zext (shl $src, pos) zero extend from i32 to i64
Patch by Violeta Vukobrat.
Differential Revision: https://reviews.llvm.org/D30464
llvm-svn: 297832
93 lines
1.8 KiB
LLVM
93 lines
1.8 KiB
LLVM
; RUN: llc -march=mips64 -mcpu=octeon -target-abi=n64 < %s -o - | FileCheck %s
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define i64 @cins_zext(i32 signext %n) {
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entry:
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%shl = shl i32 %n, 5
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%conv = zext i32 %shl to i64
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ret i64 %conv
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; CHECK-LABEL: cins_zext:
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; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 5, 26
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}
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define i64 @cins_and_shl(i64 zeroext %n) {
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entry:
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%and = shl i64 %n, 8
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%shl = and i64 %and, 16776960
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ret i64 %shl
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; CHECK-LABEL: cins_and_shl:
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; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 8, 15
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}
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define i64 @cins_and_shl32(i64 zeroext %n) {
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entry:
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%and = shl i64 %n, 38
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%shl = and i64 %and, 18014123631575040
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ret i64 %shl
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; CHECK-LABEL: cins_and_shl32:
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; CHECK: cins32 $[[R0:[0-9]+]], $[[R1:[0-9]+]], 6, 15
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}
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define zeroext i16 @cins_and_shl_16(i16 zeroext %n) {
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entry:
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%0 = shl i16 %n, 2
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%1 = and i16 %0, 60
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ret i16 %1
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; CHECK-LABEL: cins_and_shl_16:
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; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 2, 3
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}
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define zeroext i8 @cins_and_shl_8(i8 zeroext %n) {
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entry:
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%0 = shl i8 %n, 2
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%1 = and i8 %0, 12
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ret i8 %1
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; CHECK-LABEL: cins_and_shl_8:
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; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 2, 1
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}
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define i32 @cins_i32(i32 signext %a) {
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entry:
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%and = shl i32 %a, 17
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%shl = and i32 %and, 536739840
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ret i32 %shl
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; CHECK-LABEL: cins_i32:
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; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 17, 11
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}
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define i64 @cins_shl_and(i32 signext %n) {
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entry:
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%and = and i32 %n, 65535
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%conv = zext i32 %and to i64
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%shl = shl nuw nsw i64 %conv, 31
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ret i64 %shl
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; CHECK-LABEL: cins_shl_and:
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; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 31, 15
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}
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define i64 @cins_shl_and32(i32 signext %n) {
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entry:
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%and = and i32 %n, 65535
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%conv = zext i32 %and to i64
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%shl = shl nuw nsw i64 %conv, 47
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ret i64 %shl
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; CHECK-LABEL: cins_shl_and32:
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; CHECK: cins32 $[[R0:[0-9]+]], $[[R1:[0-9]+]], 15, 15
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}
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