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82d9e3d26c
There are some VectorShuffle Nodes in SDAG which can be selected to XXSLDWI instruction, this patch recognizes them and does the selection to improve the PPC performance. llvm-svn: 303822
30 lines
896 B
LLVM
30 lines
896 B
LLVM
; RUN: llc -verify-machineinstrs < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind
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define <2 x i32> @test1(<4 x i32> %wide.vec) #0 {
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entry:
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%strided.vec = shufflevector <4 x i32> %wide.vec, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
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ret <2 x i32> %strided.vec
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; CHECK-LABEL: @test1
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; CHECK: xxswapd 35, 34
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; CHECK: vmrghw 2, 2, 3
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; CHECK: blr
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}
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; Function Attrs: nounwind
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define <16 x i8> @test2(<16 x i8> %wide.vec) #0 {
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entry:
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%strided.vec = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 9, i32 10, i32 11>
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ret <16 x i8> %strided.vec
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; CHECK-LABEL: @test2
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; CHECK: xxsldwi 34, 34, 34, 3
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; CHECK: blr
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}
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attributes #0 = { nounwind "target-cpu"="pwr7" }
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