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262321d1ff
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"
For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"
Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.
Differential Revision: https://reviews.llvm.org/D38851
llvm-svn: 316101
70 lines
2.7 KiB
LLVM
70 lines
2.7 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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target triple = "hexagon-unknown--elf"
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; Check that we can predicate base+offset vector stores.
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; CHECK-LABEL: sammy
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; CHECK: if{{.*}}vmem(r{{[0-9]+}}+#0) =
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define void @sammy(<16 x i32>* nocapture %p, <16 x i32>* nocapture readonly %q, i32 %n) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* %q, align 64
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%sub = add nsw i32 %n, -1
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br label %for.body
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for.body: ; preds = %if.end, %entry
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%p.addr.011 = phi <16 x i32>* [ %p, %entry ], [ %incdec.ptr, %if.end ]
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%i.010 = phi i32 [ 0, %entry ], [ %add, %if.end ]
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%mul = mul nsw i32 %i.010, %sub
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%add = add nuw nsw i32 %i.010, 1
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%mul1 = mul nsw i32 %add, %n
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%cmp2 = icmp slt i32 %mul, %mul1
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br i1 %cmp2, label %if.then, label %if.end
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if.then: ; preds = %for.body
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store <16 x i32> %0, <16 x i32>* %p.addr.011, align 64
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br label %if.end
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if.end: ; preds = %if.then, %for.body
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%incdec.ptr = getelementptr inbounds <16 x i32>, <16 x i32>* %p.addr.011, i32 1
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%exitcond = icmp eq i32 %add, 100
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %if.end
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ret void
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}
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; Check that we can predicate post-increment vector stores.
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; CHECK-LABEL: danny
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; CHECK: if{{.*}}vmem(r{{[0-9]+}}++#1) =
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define void @danny(<16 x i32>* nocapture %p, <16 x i32>* nocapture readonly %q, i32 %n) #0 {
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entry:
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%0 = load <16 x i32>, <16 x i32>* %q, align 64
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%sub = add nsw i32 %n, -1
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br label %for.body
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for.body: ; preds = %if.end, %entry
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%p.addr.012 = phi <16 x i32>* [ %p, %entry ], [ %incdec.ptr3, %if.end ]
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%i.011 = phi i32 [ 0, %entry ], [ %add, %if.end ]
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%mul = mul nsw i32 %i.011, %sub
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%add = add nuw nsw i32 %i.011, 1
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%mul1 = mul nsw i32 %add, %n
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%cmp2 = icmp slt i32 %mul, %mul1
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br i1 %cmp2, label %if.then, label %if.end
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if.then: ; preds = %for.body
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%incdec.ptr = getelementptr inbounds <16 x i32>, <16 x i32>* %p.addr.012, i32 1
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store <16 x i32> %0, <16 x i32>* %p.addr.012, align 64
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br label %if.end
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if.end: ; preds = %if.then, %for.body
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%p.addr.1 = phi <16 x i32>* [ %incdec.ptr, %if.then ], [ %p.addr.012, %for.body ]
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%incdec.ptr3 = getelementptr inbounds <16 x i32>, <16 x i32>* %p.addr.1, i32 1
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%exitcond = icmp eq i32 %add, 100
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %if.end
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ret void
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}
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attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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