Ana Pazos 34c01577a9 [RISCV] Fixed Assertion`Kind == Immediate && "Invalid type access!"' failed. ... Summary: Missing check for isImm() in some Immediate classes. This bug was uncovered by a LLVM MC Assembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: hiraditya, asb Reviewed By: hiraditya, asb Subscribers: llvm-commits, hiraditya, kito-cheng, shiva0217, rkruppe, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei Differential Revision: https://reviews.llvm.org/D50797 llvm-svn: 340674		2018-08-24 23:47:49 +00:00
..
cnop.s
compress-cjal.s
compress-rv32d.s
compress-rv32f.s
compress-rv32i.s	[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0	2018-04-12 19:22:40 +00:00
compress-rv64i.s
compressed-relocations.s	[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced	2018-05-18 06:42:21 +00:00
csr-aliases.s
data-directives-invalid.s	[RISCV] Add support for .half, .hword, .word, .dword directives	2018-05-17 05:58:08 +00:00
data-directives-valid.s	[RISCV] Add support for .half, .hword, .word, .dword directives	2018-05-17 05:58:08 +00:00
elf-flags.s
elf-header.s
fixups-compressed.s
fixups-diagnostics.s
fixups-expr.s	[RISCV] Add symbol diff relocation support for RISC-V	2018-05-23 12:36:18 +00:00
fixups.s	[RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table	2018-05-30 01:16:36 +00:00
function-call-invalid.s	[RISCV] Support "call" pseudoinstruction in the MC layer	2018-04-25 14:18:55 +00:00
function-call.s	[RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table	2018-05-30 01:16:36 +00:00
hilo-constaddr-expr.s	[RISCV] Add symbol diff relocation support for RISC-V	2018-05-23 12:36:18 +00:00
hilo-constaddr.s	[RISCV] Add symbol diff relocation support for RISC-V	2018-05-23 12:36:18 +00:00
linker-relaxation.s	[RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table	2018-05-30 01:16:36 +00:00
lit.local.cfg
lla-invalid.s	[RISCV] Add "lla" pseudo-instruction to assembler	2018-08-09 07:08:20 +00:00
option-invalid.s	[RISCV] Support .option rvc and norvc assembler directives	2018-05-11 17:30:28 +00:00
option-rvc.s	[RISCV] Support .option rvc and norvc assembler directives	2018-05-11 17:30:28 +00:00
priv-invalid.s
priv-valid.s
relocations.s
rv32-relaxation.s	[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced	2018-05-18 06:42:21 +00:00
rv32a-invalid.s
rv32a-valid.s
rv32c-aliases-valid.s	[RISC-V] Fixed alias for addi x2, x2, 0	2018-08-09 20:51:53 +00:00
rv32c-fuzzed-invalid.s	[RISCV] Fixed Assertion`Kind == Immediate && "Invalid type access!"' failed.	2018-08-24 23:47:49 +00:00
rv32c-invalid.s
rv32c-only-valid.s
rv32c-valid.s
rv32d-invalid.s
rv32d-valid.s
rv32dc-invalid.s
rv32dc-valid.s
rv32f-invalid.s
rv32f-valid.s
rv32fc-invalid.s
rv32fc-valid.s
rv32i-aliases-invalid.s	[RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate	2018-08-08 14:45:44 +00:00
rv32i-aliases-valid.s	[RISCV] AsmParser support for the li pseudo instruction	2018-06-07 15:35:47 +00:00
rv32i-invalid.s	[RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate	2018-08-08 14:45:44 +00:00
rv32i-valid.s	[RISCV] Implement MC layer support for the fence.tso instruction	2018-06-08 10:39:05 +00:00
rv32m-invalid.s
rv32m-valid.s
rv64-relaxation.s	[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced	2018-05-18 06:42:21 +00:00
rv64a-invalid.s
rv64a-valid.s
rv64c-aliases-valid.s	[RISCV] AsmParser support for the li pseudo instruction	2018-06-07 15:35:47 +00:00
rv64c-invalid.s
rv64c-valid.s
rv64d-aliases-valid.s
rv64d-invalid.s
rv64d-valid.s
rv64dc-valid.s
rv64f-aliases-valid.s
rv64f-invalid.s
rv64f-valid.s
rv64i-aliases-invalid.s	[RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate	2018-08-08 14:45:44 +00:00
rv64i-aliases-valid.s	[RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate	2018-08-08 14:45:44 +00:00
rv64i-invalid.s
rv64i-valid.s
rv64m-valid.s
rvd-aliases-valid.s	[RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d}	2018-06-20 14:03:02 +00:00
rvf-aliases-valid.s	[RISCV] Accept fmv.s.x and fmv.x.s as mnemonic aliases for fmv.w.x and fmv.x.w	2018-06-20 18:42:25 +00:00
rvi-aliases-valid.s	[RISCV] Add mnemonic alias: move, sbreak and scall.	2018-08-08 14:53:45 +00:00
rvi-pseudos.s	[RISCV] Add "lla" pseudo-instruction to assembler	2018-08-09 07:08:20 +00:00
tail-call-invalid.s	[RISCV] Implement MC layer support for the tail pseudoinstruction	2018-05-17 17:31:27 +00:00
tail-call.s	[RISCV] Tail calls don't need to save return address	2018-06-21 14:37:09 +00:00