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a7927697c9
This pseudo-instruction is similar to la but uses PC-relative addressing unconditionally. This is, la is only different to lla when using -fPIC. This pseudo-instruction seems often forgotten in several specs but it is definitely mentioned in binutils opcodes/riscv-opc.c. The semantics are defined both in page 37 of the "RISC-V Reader" book but also in function macro found in gas/config/tc-riscv.c. This is a very first step towards adding PIC support for Linux in the RISC-V backend. The lla pseudo-instruction expands to a sequence of auipc + addi with a couple of pc-rel relocations where the second points to the first one. This is described in https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses For now, this patch only introduces support of that pseudo instruction at the assembler parser. Differential Revision: https://reviews.llvm.org/D49661 llvm-svn: 339314
29 lines
784 B
ArmAsm
29 lines
784 B
ArmAsm
# RUN: llvm-mc %s -triple=riscv32 | FileCheck %s
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# RUN: llvm-mc %s -triple=riscv64 | FileCheck %s
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# CHECK: .Lpcrel_hi0:
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# CHECK: auipc a0, %pcrel_hi(a_symbol)
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# CHECK: addi a0, a0, %pcrel_lo(.Lpcrel_hi0)
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lla a0, a_symbol
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# CHECK: .Lpcrel_hi1:
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# CHECK: auipc a1, %pcrel_hi(another_symbol)
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# CHECK: addi a1, a1, %pcrel_lo(.Lpcrel_hi1)
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lla a1, another_symbol
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# Check that we can load the address of symbols that are spelled like a register
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# CHECK: .Lpcrel_hi2:
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# CHECK: auipc a2, %pcrel_hi(zero)
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# CHECK: addi a2, a2, %pcrel_lo(.Lpcrel_hi2)
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lla a2, zero
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# CHECK: .Lpcrel_hi3:
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# CHECK: auipc a3, %pcrel_hi(ra)
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# CHECK: addi a3, a3, %pcrel_lo(.Lpcrel_hi3)
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lla a3, ra
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# CHECK: .Lpcrel_hi4:
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# CHECK: auipc a4, %pcrel_hi(f1)
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# CHECK: addi a4, a4, %pcrel_lo(.Lpcrel_hi4)
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lla a4, f1
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