Sanjay Patel e49c68f164 [x86, AVX] add test file to show vzeroupper pass excesses ... llvm-svn: 270375		2016-05-22 19:55:48 +00:00
..
AArch64	[AArch64] Disable narrow load merge by default	2016-05-20 18:45:49 +00:00
AMDGPU	AMDGPU: Define priorities for register classes	2016-05-21 03:55:07 +00:00
ARM	[ARM, AArch64] Match additional patterns to ldN instructions	2016-05-19 21:39:00 +00:00
BPF	[llc] New diagnostic handler	2016-05-16 14:28:02 +00:00
Generic
Hexagon	When looking for a spill slot in reg scavenger, find one that matches RC	2016-05-18 18:16:00 +00:00
Inputs
Lanai	[lanai] Change reloc to use PIC_ by default and cleanup.	2016-05-20 21:41:53 +00:00
Mips	[mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine verifier.	2016-05-19 10:42:14 +00:00
MIR	[llc] New diagnostic handler	2016-05-16 14:28:02 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Add a testcase for TCO on string rvo function	2016-05-20 22:42:01 +00:00
SPARC	[Sparc] Enable more inline assembly constraints.	2016-05-20 09:03:01 +00:00
SystemZ	[SystemZ] Fix register ordering for BinaryRRF instructions	2016-05-18 13:24:57 +00:00
Thumb
Thumb2
WebAssembly	[WebAssembly] Optimize away return instructions using fallthroughs.	2016-05-21 00:21:56 +00:00
WinEH
X86	[x86, AVX] add test file to show vzeroupper pass excesses	2016-05-22 19:55:48 +00:00
XCore