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1380494168
* Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! llvm-svn: 155704
13 lines
338 B
LLVM
13 lines
338 B
LLVM
; RUN: llc < %s -march=x86 -mcpu=pentiumpro | FileCheck %s
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; PR1012
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define float @foo(float* %col.2.0) {
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; CHECK: fucompi
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; CHECK: fcmov
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%tmp = load float* %col.2.0
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%tmp16 = fcmp olt float %tmp, 0.000000e+00
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%tmp20 = fsub float -0.000000e+00, %tmp
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%iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp
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ret float %iftmp.2.0
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}
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