mirror of
https://github.com/RPCS3/llvm-mirror.git
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e0c4d702bd
Pre-P8, when we generate code for unaligned vector loads (for Altivec and QPX types), even when accounting for the combining that takes place for multiple consecutive such loads, there is at least one load instructions and one permutation for each load. Make sure the cost reported reflects the cost of the permutes as well. llvm-svn: 246807
405 lines
11 KiB
LLVM
405 lines
11 KiB
LLVM
; RUN: opt < %s -cost-model -analyze | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define <16 x i8> @test_l_v16i8(<16 x i8>* %p) #0 {
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entry:
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%r = load <16 x i8>, <16 x i8>* %p, align 1
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ret <16 x i8> %r
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; CHECK-LABEL: test_l_v16i8
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; CHECK: cost of 2 for instruction: %r = load <16 x i8>, <16 x i8>* %p, align 1
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}
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define <32 x i8> @test_l_v32i8(<32 x i8>* %p) #0 {
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entry:
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%r = load <32 x i8>, <32 x i8>* %p, align 1
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ret <32 x i8> %r
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; CHECK-LABEL: test_l_v32i8
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; CHECK: cost of 4 for instruction: %r = load <32 x i8>, <32 x i8>* %p, align 1
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}
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define <8 x i16> @test_l_v8i16(<8 x i16>* %p) #0 {
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entry:
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%r = load <8 x i16>, <8 x i16>* %p, align 2
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ret <8 x i16> %r
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; CHECK-LABEL: test_l_v8i16
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; CHECK: cost of 2 for instruction: %r = load <8 x i16>, <8 x i16>* %p, align 2
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}
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define <16 x i16> @test_l_v16i16(<16 x i16>* %p) #0 {
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entry:
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%r = load <16 x i16>, <16 x i16>* %p, align 2
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ret <16 x i16> %r
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; CHECK-LABEL: test_l_v16i16
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; CHECK: cost of 4 for instruction: %r = load <16 x i16>, <16 x i16>* %p, align 2
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}
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define <4 x i32> @test_l_v4i32(<4 x i32>* %p) #0 {
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entry:
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%r = load <4 x i32>, <4 x i32>* %p, align 4
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ret <4 x i32> %r
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; CHECK-LABEL: test_l_v4i32
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; CHECK: cost of 2 for instruction: %r = load <4 x i32>, <4 x i32>* %p, align 4
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}
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define <8 x i32> @test_l_v8i32(<8 x i32>* %p) #0 {
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entry:
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%r = load <8 x i32>, <8 x i32>* %p, align 4
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ret <8 x i32> %r
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; CHECK-LABEL: test_l_v8i32
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; CHECK: cost of 4 for instruction: %r = load <8 x i32>, <8 x i32>* %p, align 4
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}
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define <2 x i64> @test_l_v2i64(<2 x i64>* %p) #0 {
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entry:
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%r = load <2 x i64>, <2 x i64>* %p, align 8
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ret <2 x i64> %r
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; CHECK-LABEL: test_l_v2i64
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; CHECK: cost of 1 for instruction: %r = load <2 x i64>, <2 x i64>* %p, align 8
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}
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define <4 x i64> @test_l_v4i64(<4 x i64>* %p) #0 {
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entry:
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%r = load <4 x i64>, <4 x i64>* %p, align 8
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ret <4 x i64> %r
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; CHECK-LABEL: test_l_v4i64
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; CHECK: cost of 2 for instruction: %r = load <4 x i64>, <4 x i64>* %p, align 8
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}
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define <4 x float> @test_l_v4float(<4 x float>* %p) #0 {
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entry:
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%r = load <4 x float>, <4 x float>* %p, align 4
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ret <4 x float> %r
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; CHECK-LABEL: test_l_v4float
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; CHECK: cost of 2 for instruction: %r = load <4 x float>, <4 x float>* %p, align 4
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}
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define <8 x float> @test_l_v8float(<8 x float>* %p) #0 {
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entry:
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%r = load <8 x float>, <8 x float>* %p, align 4
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ret <8 x float> %r
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; CHECK-LABEL: test_l_v8float
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; CHECK: cost of 4 for instruction: %r = load <8 x float>, <8 x float>* %p, align 4
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}
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define <2 x double> @test_l_v2double(<2 x double>* %p) #0 {
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entry:
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%r = load <2 x double>, <2 x double>* %p, align 8
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ret <2 x double> %r
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; CHECK-LABEL: test_l_v2double
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; CHECK: cost of 1 for instruction: %r = load <2 x double>, <2 x double>* %p, align 8
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}
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define <4 x double> @test_l_v4double(<4 x double>* %p) #0 {
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entry:
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%r = load <4 x double>, <4 x double>* %p, align 8
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ret <4 x double> %r
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; CHECK-LABEL: test_l_v4double
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; CHECK: cost of 2 for instruction: %r = load <4 x double>, <4 x double>* %p, align 8
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}
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define <16 x i8> @test_l_p8v16i8(<16 x i8>* %p) #2 {
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entry:
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%r = load <16 x i8>, <16 x i8>* %p, align 1
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ret <16 x i8> %r
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; CHECK-LABEL: test_l_p8v16i8
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; CHECK: cost of 1 for instruction: %r = load <16 x i8>, <16 x i8>* %p, align 1
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}
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define <32 x i8> @test_l_p8v32i8(<32 x i8>* %p) #2 {
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entry:
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%r = load <32 x i8>, <32 x i8>* %p, align 1
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ret <32 x i8> %r
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; CHECK-LABEL: test_l_p8v32i8
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; CHECK: cost of 2 for instruction: %r = load <32 x i8>, <32 x i8>* %p, align 1
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}
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define <8 x i16> @test_l_p8v8i16(<8 x i16>* %p) #2 {
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entry:
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%r = load <8 x i16>, <8 x i16>* %p, align 2
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ret <8 x i16> %r
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; CHECK-LABEL: test_l_p8v8i16
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; CHECK: cost of 1 for instruction: %r = load <8 x i16>, <8 x i16>* %p, align 2
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}
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define <16 x i16> @test_l_p8v16i16(<16 x i16>* %p) #2 {
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entry:
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%r = load <16 x i16>, <16 x i16>* %p, align 2
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ret <16 x i16> %r
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; CHECK-LABEL: test_l_p8v16i16
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; CHECK: cost of 2 for instruction: %r = load <16 x i16>, <16 x i16>* %p, align 2
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}
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define <4 x i32> @test_l_p8v4i32(<4 x i32>* %p) #2 {
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entry:
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%r = load <4 x i32>, <4 x i32>* %p, align 4
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ret <4 x i32> %r
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; CHECK-LABEL: test_l_p8v4i32
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; CHECK: cost of 1 for instruction: %r = load <4 x i32>, <4 x i32>* %p, align 4
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}
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define <8 x i32> @test_l_p8v8i32(<8 x i32>* %p) #2 {
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entry:
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%r = load <8 x i32>, <8 x i32>* %p, align 4
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ret <8 x i32> %r
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; CHECK-LABEL: test_l_p8v8i32
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; CHECK: cost of 2 for instruction: %r = load <8 x i32>, <8 x i32>* %p, align 4
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}
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define <2 x i64> @test_l_p8v2i64(<2 x i64>* %p) #2 {
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entry:
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%r = load <2 x i64>, <2 x i64>* %p, align 8
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ret <2 x i64> %r
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; CHECK-LABEL: test_l_p8v2i64
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; CHECK: cost of 1 for instruction: %r = load <2 x i64>, <2 x i64>* %p, align 8
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}
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define <4 x i64> @test_l_p8v4i64(<4 x i64>* %p) #2 {
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entry:
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%r = load <4 x i64>, <4 x i64>* %p, align 8
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ret <4 x i64> %r
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; CHECK-LABEL: test_l_p8v4i64
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; CHECK: cost of 2 for instruction: %r = load <4 x i64>, <4 x i64>* %p, align 8
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}
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define <4 x float> @test_l_p8v4float(<4 x float>* %p) #2 {
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entry:
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%r = load <4 x float>, <4 x float>* %p, align 4
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ret <4 x float> %r
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; CHECK-LABEL: test_l_p8v4float
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; CHECK: cost of 1 for instruction: %r = load <4 x float>, <4 x float>* %p, align 4
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}
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define <8 x float> @test_l_p8v8float(<8 x float>* %p) #2 {
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entry:
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%r = load <8 x float>, <8 x float>* %p, align 4
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ret <8 x float> %r
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; CHECK-LABEL: test_l_p8v8float
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; CHECK: cost of 2 for instruction: %r = load <8 x float>, <8 x float>* %p, align 4
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}
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define <2 x double> @test_l_p8v2double(<2 x double>* %p) #2 {
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entry:
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%r = load <2 x double>, <2 x double>* %p, align 8
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ret <2 x double> %r
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; CHECK-LABEL: test_l_p8v2double
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; CHECK: cost of 1 for instruction: %r = load <2 x double>, <2 x double>* %p, align 8
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}
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define <4 x double> @test_l_p8v4double(<4 x double>* %p) #2 {
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entry:
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%r = load <4 x double>, <4 x double>* %p, align 8
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ret <4 x double> %r
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; CHECK-LABEL: test_l_p8v4double
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; CHECK: cost of 2 for instruction: %r = load <4 x double>, <4 x double>* %p, align 8
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}
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define <4 x float> @test_l_qv4float(<4 x float>* %p) #1 {
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entry:
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%r = load <4 x float>, <4 x float>* %p, align 4
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ret <4 x float> %r
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; CHECK-LABEL: test_l_qv4float
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; CHECK: cost of 2 for instruction: %r = load <4 x float>, <4 x float>* %p, align 4
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}
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define <8 x float> @test_l_qv8float(<8 x float>* %p) #1 {
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entry:
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%r = load <8 x float>, <8 x float>* %p, align 4
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ret <8 x float> %r
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; CHECK-LABEL: test_l_qv8float
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; CHECK: cost of 4 for instruction: %r = load <8 x float>, <8 x float>* %p, align 4
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}
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define <4 x double> @test_l_qv4double(<4 x double>* %p) #1 {
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entry:
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%r = load <4 x double>, <4 x double>* %p, align 8
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ret <4 x double> %r
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; CHECK-LABEL: test_l_qv4double
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; CHECK: cost of 2 for instruction: %r = load <4 x double>, <4 x double>* %p, align 8
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}
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define <8 x double> @test_l_qv8double(<8 x double>* %p) #1 {
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entry:
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%r = load <8 x double>, <8 x double>* %p, align 8
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ret <8 x double> %r
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; CHECK-LABEL: test_l_qv8double
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; CHECK: cost of 4 for instruction: %r = load <8 x double>, <8 x double>* %p, align 8
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}
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define void @test_s_v16i8(<16 x i8>* %p, <16 x i8> %v) #0 {
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entry:
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store <16 x i8> %v, <16 x i8>* %p, align 1
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ret void
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; CHECK-LABEL: test_s_v16i8
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; CHECK: cost of 1 for instruction: store <16 x i8> %v, <16 x i8>* %p, align 1
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}
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define void @test_s_v32i8(<32 x i8>* %p, <32 x i8> %v) #0 {
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entry:
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store <32 x i8> %v, <32 x i8>* %p, align 1
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ret void
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; CHECK-LABEL: test_s_v32i8
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; CHECK: cost of 2 for instruction: store <32 x i8> %v, <32 x i8>* %p, align 1
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}
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define void @test_s_v8i16(<8 x i16>* %p, <8 x i16> %v) #0 {
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entry:
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store <8 x i16> %v, <8 x i16>* %p, align 2
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ret void
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; CHECK-LABEL: test_s_v8i16
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; CHECK: cost of 1 for instruction: store <8 x i16> %v, <8 x i16>* %p, align 2
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}
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define void @test_s_v16i16(<16 x i16>* %p, <16 x i16> %v) #0 {
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entry:
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store <16 x i16> %v, <16 x i16>* %p, align 2
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ret void
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; CHECK-LABEL: test_s_v16i16
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; CHECK: cost of 2 for instruction: store <16 x i16> %v, <16 x i16>* %p, align 2
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}
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define void @test_s_v4i32(<4 x i32>* %p, <4 x i32> %v) #0 {
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entry:
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store <4 x i32> %v, <4 x i32>* %p, align 4
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ret void
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; CHECK-LABEL: test_s_v4i32
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; CHECK: cost of 1 for instruction: store <4 x i32> %v, <4 x i32>* %p, align 4
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}
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define void @test_s_v8i32(<8 x i32>* %p, <8 x i32> %v) #0 {
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entry:
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store <8 x i32> %v, <8 x i32>* %p, align 4
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ret void
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; CHECK-LABEL: test_s_v8i32
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; CHECK: cost of 2 for instruction: store <8 x i32> %v, <8 x i32>* %p, align 4
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}
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define void @test_s_v2i64(<2 x i64>* %p, <2 x i64> %v) #0 {
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entry:
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store <2 x i64> %v, <2 x i64>* %p, align 8
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ret void
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; CHECK-LABEL: test_s_v2i64
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; CHECK: cost of 1 for instruction: store <2 x i64> %v, <2 x i64>* %p, align 8
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}
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define void @test_s_v4i64(<4 x i64>* %p, <4 x i64> %v) #0 {
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entry:
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store <4 x i64> %v, <4 x i64>* %p, align 8
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ret void
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; CHECK-LABEL: test_s_v4i64
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; CHECK: cost of 2 for instruction: store <4 x i64> %v, <4 x i64>* %p, align 8
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}
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define void @test_s_v4float(<4 x float>* %p, <4 x float> %v) #0 {
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entry:
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store <4 x float> %v, <4 x float>* %p, align 4
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ret void
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; CHECK-LABEL: test_s_v4float
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; CHECK: cost of 1 for instruction: store <4 x float> %v, <4 x float>* %p, align 4
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}
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define void @test_s_v8float(<8 x float>* %p, <8 x float> %v) #0 {
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entry:
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store <8 x float> %v, <8 x float>* %p, align 4
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ret void
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; CHECK-LABEL: test_s_v8float
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; CHECK: cost of 2 for instruction: store <8 x float> %v, <8 x float>* %p, align 4
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}
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define void @test_s_v2double(<2 x double>* %p, <2 x double> %v) #0 {
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entry:
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store <2 x double> %v, <2 x double>* %p, align 8
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ret void
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; CHECK-LABEL: test_s_v2double
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; CHECK: cost of 1 for instruction: store <2 x double> %v, <2 x double>* %p, align 8
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}
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define void @test_s_v4double(<4 x double>* %p, <4 x double> %v) #0 {
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entry:
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store <4 x double> %v, <4 x double>* %p, align 8
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ret void
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; CHECK-LABEL: test_s_v4double
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; CHECK: cost of 2 for instruction: store <4 x double> %v, <4 x double>* %p, align 8
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}
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define void @test_s_qv4float(<4 x float>* %p, <4 x float> %v) #1 {
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entry:
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store <4 x float> %v, <4 x float>* %p, align 4
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ret void
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; CHECK-LABEL: test_s_qv4float
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; CHECK: cost of 7 for instruction: store <4 x float> %v, <4 x float>* %p, align 4
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}
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define void @test_s_qv8float(<8 x float>* %p, <8 x float> %v) #1 {
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entry:
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store <8 x float> %v, <8 x float>* %p, align 4
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ret void
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; CHECK-LABEL: test_s_qv8float
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; CHECK: cost of 15 for instruction: store <8 x float> %v, <8 x float>* %p, align 4
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}
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define void @test_s_qv4double(<4 x double>* %p, <4 x double> %v) #1 {
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entry:
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store <4 x double> %v, <4 x double>* %p, align 8
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ret void
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; CHECK-LABEL: test_s_qv4double
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; CHECK: cost of 7 for instruction: store <4 x double> %v, <4 x double>* %p, align 8
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}
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define void @test_s_qv8double(<8 x double>* %p, <8 x double> %v) #1 {
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entry:
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store <8 x double> %v, <8 x double>* %p, align 8
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ret void
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; CHECK-LABEL: test_s_qv8double
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; CHECK: cost of 15 for instruction: store <8 x double> %v, <8 x double>* %p, align 8
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}
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attributes #0 = { nounwind "target-cpu"="pwr7" }
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attributes #1 = { nounwind "target-cpu"="a2q" }
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attributes #2 = { nounwind "target-cpu"="pwr8" }
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