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c7495a0fca
Add a mapping from register-based <INSN>R instructions to the corresponding memory-based <INSN>. Use it to cut down on the number of spill loads. Some instructions extend their operands from smaller fields, so this required a new TSFlags field to say how big the unextended operand is. This optimisation doesn't trigger for C(G)R and CL(G)R because in practice we always combine those instructions with a branch. Adding a test for every other case probably seems excessive, but it did catch a missed optimisation for DSGF (fixed in r185435). llvm-svn: 185529
120 lines
3.1 KiB
LLVM
120 lines
3.1 KiB
LLVM
; Test 32-bit floating-point addition.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare float @foo()
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; Check register addition.
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define float @f1(float %f1, float %f2) {
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; CHECK: f1:
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; CHECK: aebr %f0, %f2
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; CHECK: br %r14
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%res = fadd float %f1, %f2
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ret float %res
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}
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; Check the low end of the AEB range.
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define float @f2(float %f1, float *%ptr) {
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; CHECK: f2:
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; CHECK: aeb %f0, 0(%r2)
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; CHECK: br %r14
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%f2 = load float *%ptr
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%res = fadd float %f1, %f2
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ret float %res
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}
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; Check the high end of the aligned AEB range.
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define float @f3(float %f1, float *%base) {
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; CHECK: f3:
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; CHECK: aeb %f0, 4092(%r2)
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; CHECK: br %r14
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%ptr = getelementptr float *%base, i64 1023
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%f2 = load float *%ptr
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%res = fadd float %f1, %f2
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ret float %res
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define float @f4(float %f1, float *%base) {
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; CHECK: f4:
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; CHECK: aghi %r2, 4096
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; CHECK: aeb %f0, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr float *%base, i64 1024
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%f2 = load float *%ptr
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%res = fadd float %f1, %f2
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ret float %res
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}
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; Check negative displacements, which also need separate address logic.
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define float @f5(float %f1, float *%base) {
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; CHECK: f5:
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; CHECK: aghi %r2, -4
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; CHECK: aeb %f0, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr float *%base, i64 -1
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%f2 = load float *%ptr
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%res = fadd float %f1, %f2
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ret float %res
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}
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; Check that AEB allows indices.
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define float @f6(float %f1, float *%base, i64 %index) {
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; CHECK: f6:
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; CHECK: sllg %r1, %r3, 2
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; CHECK: aeb %f0, 400(%r1,%r2)
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; CHECK: br %r14
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%ptr1 = getelementptr float *%base, i64 %index
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%ptr2 = getelementptr float *%ptr1, i64 100
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%f2 = load float *%ptr2
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%res = fadd float %f1, %f2
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ret float %res
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}
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; Check that additions of spilled values can use AEB rather than AEBR.
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define float @f7(float *%ptr0) {
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; CHECK: f7:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: aeb %f0, 16{{[04]}}(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr float *%ptr0, i64 2
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%ptr2 = getelementptr float *%ptr0, i64 4
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%ptr3 = getelementptr float *%ptr0, i64 6
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%ptr4 = getelementptr float *%ptr0, i64 8
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%ptr5 = getelementptr float *%ptr0, i64 10
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%ptr6 = getelementptr float *%ptr0, i64 12
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%ptr7 = getelementptr float *%ptr0, i64 14
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%ptr8 = getelementptr float *%ptr0, i64 16
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%ptr9 = getelementptr float *%ptr0, i64 18
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%ptr10 = getelementptr float *%ptr0, i64 20
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%val0 = load float *%ptr0
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%val1 = load float *%ptr1
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%val2 = load float *%ptr2
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%val3 = load float *%ptr3
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%val4 = load float *%ptr4
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%val5 = load float *%ptr5
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%val6 = load float *%ptr6
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%val7 = load float *%ptr7
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%val8 = load float *%ptr8
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%val9 = load float *%ptr9
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%val10 = load float *%ptr10
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%ret = call float @foo()
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%add0 = fadd float %ret, %val0
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%add1 = fadd float %add0, %val1
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%add2 = fadd float %add1, %val2
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%add3 = fadd float %add2, %val3
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%add4 = fadd float %add3, %val4
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%add5 = fadd float %add4, %val5
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%add6 = fadd float %add5, %val6
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%add7 = fadd float %add6, %val7
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%add8 = fadd float %add7, %val8
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%add9 = fadd float %add8, %val9
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%add10 = fadd float %add9, %val10
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ret float %add10
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}
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