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2b831fb8d3
The VDUP instruction source register doesn't allow a non-constant lane index, so make sure we don't construct a ARM::VDUPLANE node asking it to do so. rdar://13328063 http://llvm.org/bugs/show_bug.cgi?id=13963 llvm-svn: 176413
15 lines
665 B
LLVM
15 lines
665 B
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
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define void @bar(<4 x i32>* %p, i32 %lane, <4 x i32> %phitmp) nounwind {
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; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[SOURCE:[0-9]+]]:128]
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; CHECK: add.w r[[ADDR:[0-9]+]], r[[SOURCE]], {{r[0-9]+}}, lsl #2
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; CHECK: vld1.32 {[[DREG:d[0-9]+]][], [[DREG2:d[0-9]+]][]}, [r[[ADDR]]:32]
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; CHECK: vst1.32 {[[DREG]], [[DREG2]]}, [r0]
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%val = extractelement <4 x i32> %phitmp, i32 %lane
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%r1 = insertelement <4 x i32> undef, i32 %val, i32 1
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%r2 = insertelement <4 x i32> %r1, i32 %val, i32 2
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%r3 = insertelement <4 x i32> %r2, i32 %val, i32 3
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store <4 x i32> %r3, <4 x i32>* %p, align 4
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ret void
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}
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