Matt Arsenault e4ccb8ba03 AMDGPU: Replace i64 add/sub lowering ... Use VOP3 add/addc like usual. This has some tradeoffs. Inline immediates fold a little better, but other constants are worse off. SIShrinkInstructions could be made smarter to handle these cases. This allows us to avoid selecting scalar adds where we need to track the carry in scc and replace its users. This makes it easier to use the carryless VALU adds. llvm-svn: 318340		2017-11-15 21:51:43 +00:00
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AArch64	[GISel]: Rework legalization algorithm for better elimination of	2017-11-14 22:42:19 +00:00
AMDGPU	AMDGPU: Replace i64 add/sub lowering	2017-11-15 21:51:43 +00:00
ARC
ARM	[GISel]: Rework legalization algorithm for better elimination of	2017-11-14 22:42:19 +00:00
AVR	[AVR] Remove the select-mbb-placement-bug.ll test	2017-11-14 04:32:49 +00:00
BPF
Generic	[CodeGen] Peel off the dominant case in switch statement in lowering	2017-11-14 21:44:09 +00:00
Hexagon
Inputs
Lanai
Mips	[mips] Improve genConstMult() to work with arbitrary precision	2017-11-15 15:24:04 +00:00
MIR
MSP430
Nios2
NVPTX
PowerPC	[PowerPC] Implement mayBeEmittedAsTailCall for PPC	2017-11-15 18:58:27 +00:00
RISCV
SPARC
SystemZ	[CodeGen] Peel off the dominant case in switch statement in lowering	2017-11-14 21:44:09 +00:00
Thumb	[ARM] Fix incorrect conversion of a tail call to an ordinary call	2017-11-14 10:36:52 +00:00
Thumb2	[arm] Fix Unnecessary reloads from GOT.	2017-11-13 20:45:38 +00:00
WebAssembly	[WebAssembly] Update cfg-stackify.ll to remove the workaround added in r318288.	2017-11-15 21:38:33 +00:00
WinEH
X86	[X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule class	2017-11-15 17:11:24 +00:00
XCore