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ce9fb34c23
These only get generated if the target supports them. If one of the variants is not legal and the other is, and it is safe to do so, the other variant will be emitted. For example on AArch32 (V8), we have scalar fminnm but not fmin. Fix up a couple of tests while we're here - one now produces better code, and the other was just plain wrong to start with. llvm-svn: 245196
379 lines
11 KiB
LLVM
379 lines
11 KiB
LLVM
; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck %s
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; scalars
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define float @fp-armv8_vminnm_o(float %a, float %b) {
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; CHECK-LABEL: "fp-armv8_vminnm_o":
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; CHECK-NOT: vcmp
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; CHECK: vminnm.f32
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%cmp = fcmp fast olt float %a, %b
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%cond = select i1 %cmp, float %a, float %b
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ret float %cond
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}
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define double @fp-armv8_vminnm_ole(double %a, double %b) {
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; CHECK-LABEL: "fp-armv8_vminnm_ole":
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; CHECK-NOT: vcmp
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; CHECK: vminnm.f64
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%cmp = fcmp fast ole double %a, %b
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%cond = select i1 %cmp, double %a, double %b
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ret double %cond
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}
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define float @fp-armv8_vminnm_o_rev(float %a, float %b) {
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; CHECK-LABEL: "fp-armv8_vminnm_o_rev":
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; CHECK-NOT: vcmp
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; CHECK: vminnm.f32
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%cmp = fcmp fast ogt float %a, %b
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%cond = select i1 %cmp, float %b, float %a
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ret float %cond
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}
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define double @fp-armv8_vminnm_oge_rev(double %a, double %b) {
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; CHECK-LABEL: "fp-armv8_vminnm_oge_rev":
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; CHECK-NOT: vcmp
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; CHECK: vminnm.f64
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%cmp = fcmp fast oge double %a, %b
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%cond = select i1 %cmp, double %b, double %a
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ret double %cond
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}
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define float @fp-armv8_vminnm_u(float %a, float %b) {
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; CHECK-LABEL: "fp-armv8_vminnm_u":
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; CHECK-NOT: vcmp
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; CHECK: vminnm.f32
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%cmp = fcmp fast ult float %a, %b
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%cond = select i1 %cmp, float %a, float %b
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ret float %cond
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}
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define float @fp-armv8_vminnm_ule(float %a, float %b) {
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; CHECK-LABEL: "fp-armv8_vminnm_ule":
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; CHECK-NOT: vcmp
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; CHECK: vminnm.f32
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%cmp = fcmp fast ule float %a, %b
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%cond = select i1 %cmp, float %a, float %b
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ret float %cond
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}
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define float @fp-armv8_vminnm_u_rev(float %a, float %b) {
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; CHECK-LABEL: "fp-armv8_vminnm_u_rev":
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; CHECK-NOT: vcmp
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; CHECK: vminnm.f32
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%cmp = fcmp fast ugt float %a, %b
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%cond = select i1 %cmp, float %b, float %a
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ret float %cond
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}
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define double @fp-armv8_vminnm_uge_rev(double %a, double %b) {
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; CHECK-LABEL: "fp-armv8_vminnm_uge_rev":
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; CHECK-NOT: vcmp
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; CHECK: vminnm.f64
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%cmp = fcmp fast uge double %a, %b
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%cond = select i1 %cmp, double %b, double %a
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ret double %cond
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}
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define float @fp-armv8_vmaxnm_o(float %a, float %b) {
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; CHECK-LABEL: "fp-armv8_vmaxnm_o":
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; CHECK-NOT: vcmp
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; CHECK: vmaxnm.f32
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%cmp = fcmp fast ogt float %a, %b
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%cond = select i1 %cmp, float %a, float %b
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ret float %cond
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}
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define float @fp-armv8_vmaxnm_oge(float %a, float %b) {
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; CHECK-LABEL: "fp-armv8_vmaxnm_oge":
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; CHECK-NOT: vcmp
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; CHECK: vmaxnm.f32
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%cmp = fcmp fast oge float %a, %b
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%cond = select i1 %cmp, float %a, float %b
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ret float %cond
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}
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define float @fp-armv8_vmaxnm_o_rev(float %a, float %b) {
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; CHECK-LABEL: "fp-armv8_vmaxnm_o_rev":
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; CHECK-NOT: vcmp
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; CHECK: vmaxnm.f32
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%cmp = fcmp fast olt float %a, %b
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%cond = select i1 %cmp, float %b, float %a
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ret float %cond
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}
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define float @fp-armv8_vmaxnm_ole_rev(float %a, float %b) {
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; CHECK-LABEL: "fp-armv8_vmaxnm_ole_rev":
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; CHECK-NOT: vcmp
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; CHECK: vmaxnm.f32
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%cmp = fcmp fast ole float %a, %b
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%cond = select i1 %cmp, float %b, float %a
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ret float %cond
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}
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define float @fp-armv8_vmaxnm_u(float %a, float %b) {
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; CHECK-LABEL: "fp-armv8_vmaxnm_u":
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; CHECK-NOT: vcmp
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; CHECK: vmaxnm.f32
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%cmp = fcmp fast ugt float %a, %b
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%cond = select i1 %cmp, float %a, float %b
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ret float %cond
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}
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define float @fp-armv8_vmaxnm_uge(float %a, float %b) {
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; CHECK-LABEL: "fp-armv8_vmaxnm_uge":
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; CHECK-NOT: vcmp
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; CHECK: vmaxnm.f32
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%cmp = fcmp fast uge float %a, %b
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%cond = select i1 %cmp, float %a, float %b
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ret float %cond
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}
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define float @fp-armv8_vmaxnm_u_rev(float %a, float %b) {
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; CHECK-LABEL: "fp-armv8_vmaxnm_u_rev":
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; CHECK-NOT: vcmp
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; CHECK: vmaxnm.f32
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%cmp = fcmp fast ult float %a, %b
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%cond = select i1 %cmp, float %b, float %a
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ret float %cond
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}
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define double @fp-armv8_vmaxnm_ule_rev(double %a, double %b) {
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; CHECK-LABEL: "fp-armv8_vmaxnm_ule_rev":
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; CHECK-NOT: vcmp
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; CHECK: vmaxnm.f64
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%cmp = fcmp fast ule double %a, %b
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%cond = select i1 %cmp, double %b, double %a
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ret double %cond
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}
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; known non-NaNs
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define float @fp-armv8_vminnm_NNNo(float %a) {
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; CHECK-LABEL: "fp-armv8_vminnm_NNNo":
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; CHECK: vminnm.f32
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; CHECK: vminnm.f32
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%cmp1 = fcmp fast olt float %a, 12.
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%cond1 = select i1 %cmp1, float %a, float 12.
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%cmp2 = fcmp fast olt float 34., %cond1
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%cond2 = select i1 %cmp2, float 34., float %cond1
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ret float %cond2
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}
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define double @fp-armv8_vminnm_NNNole(double %a) {
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; CHECK-LABEL: "fp-armv8_vminnm_NNNole":
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; CHECK: vminnm.f64
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; CHECK: vminnm.f64
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%cmp1 = fcmp fast ole double %a, 34.
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%cond1 = select i1 %cmp1, double %a, double 34.
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%cmp2 = fcmp fast ole double 56., %cond1
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%cond2 = select i1 %cmp2, double 56., double %cond1
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ret double %cond2
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}
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define float @fp-armv8_vminnm_NNNo_rev(float %a) {
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; CHECK-LABEL: "fp-armv8_vminnm_NNNo_rev":
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; CHECK: vminnm.f32
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; CHECK: vminnm.f32
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%cmp1 = fcmp fast ogt float %a, 56.
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%cond1 = select i1 %cmp1, float 56., float %a
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%cmp2 = fcmp fast ogt float 78., %cond1
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%cond2 = select i1 %cmp2, float %cond1, float 78.
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ret float %cond2
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}
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define double @fp-armv8_vminnm_NNNoge_rev(double %a) {
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; CHECK-LABEL: "fp-armv8_vminnm_NNNoge_rev":
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; CHECK: vminnm.f64
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; CHECK: vminnm.f64
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%cmp1 = fcmp fast oge double %a, 78.
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%cond1 = select i1 %cmp1, double 78., double %a
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%cmp2 = fcmp fast oge double 90., %cond1
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%cond2 = select i1 %cmp2, double %cond1, double 90.
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ret double %cond2
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}
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define float @fp-armv8_vminnm_NNNu(float %b) {
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; CHECK-LABEL: "fp-armv8_vminnm_NNNu":
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; CHECK: vminnm.f32
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; CHECK: vminnm.f32
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%cmp1 = fcmp fast ult float 12., %b
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%cond1 = select i1 %cmp1, float 12., float %b
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%cmp2 = fcmp fast ult float %cond1, 34.
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%cond2 = select i1 %cmp2, float %cond1, float 34.
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ret float %cond2
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}
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define float @fp-armv8_vminnm_NNNule(float %b) {
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; CHECK-LABEL: "fp-armv8_vminnm_NNNule":
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; CHECK: vminnm.f32
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; CHECK: vminnm.f32
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%cmp1 = fcmp fast ule float 34., %b
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%cond1 = select i1 %cmp1, float 34., float %b
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%cmp2 = fcmp fast ule float %cond1, 56.
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%cond2 = select i1 %cmp2, float %cond1, float 56.
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ret float %cond2
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}
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define float @fp-armv8_vminnm_NNNu_rev(float %b) {
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; CHECK-LABEL: "fp-armv8_vminnm_NNNu_rev":
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; CHECK: vminnm.f32
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; CHECK: vminnm.f32
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%cmp1 = fcmp fast ugt float 56., %b
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%cond1 = select i1 %cmp1, float %b, float 56.
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%cmp2 = fcmp fast ugt float %cond1, 78.
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%cond2 = select i1 %cmp2, float 78., float %cond1
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ret float %cond2
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}
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define double @fp-armv8_vminnm_NNNuge_rev(double %b) {
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; CHECK-LABEL: "fp-armv8_vminnm_NNNuge_rev":
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; CHECK: vminnm.f64
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; CHECK: vminnm.f64
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%cmp1 = fcmp fast uge double 78., %b
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%cond1 = select i1 %cmp1, double %b, double 78.
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%cmp2 = fcmp fast uge double %cond1, 90.
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%cond2 = select i1 %cmp2, double 90., double %cond1
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ret double %cond2
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}
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define float @fp-armv8_vmaxnm_NNNo(float %a) {
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; CHECK-LABEL: "fp-armv8_vmaxnm_NNNo":
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; CHECK: vmaxnm.f32
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; CHECK: vmaxnm.f32
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%cmp1 = fcmp fast ogt float %a, 12.
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%cond1 = select i1 %cmp1, float %a, float 12.
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%cmp2 = fcmp fast ogt float 34., %cond1
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%cond2 = select i1 %cmp2, float 34., float %cond1
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ret float %cond2
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}
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define float @fp-armv8_vmaxnm_NNNoge(float %a) {
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; CHECK-LABEL: "fp-armv8_vmaxnm_NNNoge":
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; CHECK: vmaxnm.f32
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; CHECK: vmaxnm.f32
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%cmp1 = fcmp fast oge float %a, 34.
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%cond1 = select i1 %cmp1, float %a, float 34.
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%cmp2 = fcmp fast oge float 56., %cond1
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%cond2 = select i1 %cmp2, float 56., float %cond1
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ret float %cond2
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}
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define float @fp-armv8_vmaxnm_NNNo_rev(float %a) {
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; CHECK-LABEL: "fp-armv8_vmaxnm_NNNo_rev":
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; CHECK: vmaxnm.f32
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; CHECK: vmaxnm.f32
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%cmp1 = fcmp fast olt float %a, 56.
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%cond1 = select i1 %cmp1, float 56., float %a
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%cmp2 = fcmp fast olt float 78., %cond1
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%cond2 = select i1 %cmp2, float %cond1, float 78.
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ret float %cond2
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}
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define float @fp-armv8_vmaxnm_NNNole_rev(float %a) {
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; CHECK-LABEL: "fp-armv8_vmaxnm_NNNole_rev":
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; CHECK: vmaxnm.f32
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; CHECK: vmaxnm.f32
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%cmp1 = fcmp fast ole float %a, 78.
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%cond1 = select i1 %cmp1, float 78., float %a
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%cmp2 = fcmp fast ole float 90., %cond1
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%cond2 = select i1 %cmp2, float %cond1, float 90.
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ret float %cond2
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}
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define float @fp-armv8_vmaxnm_NNNu(float %b) {
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; CHECK-LABEL: "fp-armv8_vmaxnm_NNNu":
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; CHECK: vmaxnm.f32
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; CHECK: vmaxnm.f32
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%cmp1 = fcmp fast ugt float 12., %b
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%cond1 = select i1 %cmp1, float 12., float %b
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%cmp2 = fcmp fast ugt float %cond1, 34.
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%cond2 = select i1 %cmp2, float %cond1, float 34.
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ret float %cond2
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}
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define float @fp-armv8_vmaxnm_NNNuge(float %b) {
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; CHECK-LABEL: "fp-armv8_vmaxnm_NNNuge":
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; CHECK: vmaxnm.f32
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; CHECK: vmaxnm.f32
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%cmp1 = fcmp fast uge float 34., %b
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%cond1 = select i1 %cmp1, float 34., float %b
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%cmp2 = fcmp fast uge float %cond1, 56.
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%cond2 = select i1 %cmp2, float %cond1, float 56.
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ret float %cond2
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}
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define float @fp-armv8_vmaxnm_NNNu_rev(float %b) {
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; CHECK-LABEL: "fp-armv8_vmaxnm_NNNu_rev":
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; CHECK: vmaxnm.f32
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; CHECK: vmaxnm.f32
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%cmp1 = fcmp fast ult float 56., %b
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%cond1 = select i1 %cmp1, float %b, float 56.
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%cmp2 = fcmp fast ult float %cond1, 78.
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%cond2 = select i1 %cmp2, float 78., float %cond1
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ret float %cond2
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}
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define double @fp-armv8_vmaxnm_NNNule_rev( double %b) {
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; CHECK-LABEL: "fp-armv8_vmaxnm_NNNule_rev":
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; CHECK: vmaxnm.f64
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; CHECK: vmaxnm.f64
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%cmp1 = fcmp fast ule double 78., %b
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%cond1 = select i1 %cmp1, double %b, double 78.
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%cmp2 = fcmp fast ule double %cond1, 90.
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%cond2 = select i1 %cmp2, double 90., double %cond1
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ret double %cond2
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}
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define float @fp-armv8_vminmaxnm_0(float %a) {
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; CHECK-LABEL: "fp-armv8_vminmaxnm_0":
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; CHECK-NOT: vcmp
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; CHECK: vminnm.f32
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; CHECK: vmaxnm.f32
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%cmp1 = fcmp fast olt float %a, 0.
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%cond1 = select i1 %cmp1, float %a, float 0.
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%cmp2 = fcmp fast ogt float %cond1, 0.
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%cond2 = select i1 %cmp2, float %cond1, float 0.
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ret float %cond2
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}
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define float @fp-armv8_vminmaxnm_neg0(float %a) {
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; CHECK-LABEL: "fp-armv8_vminmaxnm_neg0":
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; CHECK-NOT: vcmp
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; CHECK: vminnm.f32
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; CHECK: vmaxnm.f32
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%cmp1 = fcmp fast olt float %a, -0.
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%cond1 = select i1 %cmp1, float %a, float -0.
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%cmp2 = fcmp fast ugt float %cond1, -0.
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%cond2 = select i1 %cmp2, float %cond1, float -0.
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ret float %cond2
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}
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define float @fp-armv8_vminmaxnm_e_0(float %a) {
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; CHECK-LABEL: "fp-armv8_vminmaxnm_e_0":
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; CHECK-NOT: vcmp
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; CHECK: vminnm.f32
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; CHECK: vmaxnm.f32
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%cmp1 = fcmp fast ule float 0., %a
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%cond1 = select i1 %cmp1, float 0., float %a
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%cmp2 = fcmp fast uge float 0., %cond1
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%cond2 = select i1 %cmp2, float 0., float %cond1
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ret float %cond2
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}
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define float @fp-armv8_vminmaxnm_e_neg0(float %a) {
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; CHECK-LABEL: "fp-armv8_vminmaxnm_e_neg0":
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; CHECK-NOT: vcmp
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; CHECK: vminnm.f32
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; CHECK: vmaxnm.f32
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%cmp1 = fcmp fast ule float -0., %a
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%cond1 = select i1 %cmp1, float -0., float %a
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%cmp2 = fcmp fast oge float -0., %cond1
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%cond2 = select i1 %cmp2, float -0., float %cond1
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ret float %cond2
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}
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declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
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