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https://github.com/RPCS3/llvm-mirror.git
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05e13f8eda
Summary: Currently clang emits these instructions via inline (volatile) asm in the CUDA headers. Switching to intrinsics will let the optimizer reason across calls to these intrinsics. Reviewers: tra Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D21160 llvm-svn: 272298
91 lines
3.5 KiB
LLVM
91 lines
3.5 KiB
LLVM
; RUN: llc < %s -march=nvptx64 -mcpu=sm_30 -disable-nvptx-favor-non-generic | FileCheck %s
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declare i32 @llvm.nvvm.shfl.down.i32(i32, i32, i32)
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declare float @llvm.nvvm.shfl.down.f32(float, i32, i32)
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declare i32 @llvm.nvvm.shfl.up.i32(i32, i32, i32)
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declare float @llvm.nvvm.shfl.up.f32(float, i32, i32)
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declare i32 @llvm.nvvm.shfl.bfly.i32(i32, i32, i32)
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declare float @llvm.nvvm.shfl.bfly.f32(float, i32, i32)
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declare i32 @llvm.nvvm.shfl.idx.i32(i32, i32, i32)
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declare float @llvm.nvvm.shfl.idx.f32(float, i32, i32)
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; Try all four permutations of register and immediate parameters with
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; shfl.down.
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; CHECK-LABEL: .func{{.*}}shfl.down1
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define i32 @shfl.down1(i32 %in) {
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; CHECK: ld.param.u32 [[IN:%r[0-9]+]]
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; CHECK: shfl.down.b32 [[OUT:%r[0-9]+]], [[IN]], 1, 2;
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; CHECK: st.param.{{.}}32 {{.*}}, [[OUT]]
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%val = call i32 @llvm.nvvm.shfl.down.i32(i32 %in, i32 1, i32 2)
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ret i32 %val
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}
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; CHECK-LABEL: .func{{.*}}shfl.down2
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define i32 @shfl.down2(i32 %in, i32 %width) {
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; CHECK: ld.param.u32 [[IN1:%r[0-9]+]]
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; CHECK: ld.param.u32 [[IN2:%r[0-9]+]]
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; CHECK: shfl.down.{{.}}32 %r{{[0-9]+}}, [[IN1]], [[IN2]], 3;
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%val = call i32 @llvm.nvvm.shfl.down.i32(i32 %in, i32 %width, i32 3)
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ret i32 %val
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}
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; CHECK-LABEL: .func{{.*}}shfl.down3
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define i32 @shfl.down3(i32 %in, i32 %mask) {
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; CHECK: ld.param.u32 [[IN1:%r[0-9]+]]
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; CHECK: ld.param.u32 [[IN2:%r[0-9]+]]
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; CHECK: shfl.down.{{.}}32 %r{{[0-9]+}}, [[IN1]], 4, [[IN2]];
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%val = call i32 @llvm.nvvm.shfl.down.i32(i32 %in, i32 4, i32 %mask)
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ret i32 %val
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}
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; CHECK-LABEL: .func{{.*}}shfl.down4
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define i32 @shfl.down4(i32 %in, i32 %width, i32 %mask) {
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; CHECK: ld.param.u32 [[IN1:%r[0-9]+]]
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; CHECK: ld.param.u32 [[IN2:%r[0-9]+]]
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; CHECK: ld.param.u32 [[IN3:%r[0-9]+]]
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; CHECK: shfl.down.{{.}}32 %r{{[0-9]+}}, [[IN1]], [[IN2]], [[IN3]];
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%val = call i32 @llvm.nvvm.shfl.down.i32(i32 %in, i32 %width, i32 %mask)
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ret i32 %val
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}
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; Try shfl.down with floating-point params.
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; CHECK-LABEL: .func{{.*}}shfl.down.float
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define float @shfl.down.float(float %in) {
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; CHECK: ld.param.f32 [[IN:%f[0-9]+]]
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; CHECK: shfl.down.b32 [[OUT:%f[0-9]+]], [[IN]], 5, 6;
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; CHECK: st.param.{{.}}32 {{.*}}, [[OUT]]
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%out = call float @llvm.nvvm.shfl.down.f32(float %in, i32 5, i32 6)
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ret float %out
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}
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; Try the rest of the shfl modes. Hopefully they're declared in such a way
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; that if shfl.down works correctly, they also work correctly.
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define void @shfl.rest(i32 %in_i32, float %in_float, i32* %out_i32, float* %out_float) {
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; CHECK: shfl.up.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 1, 2;
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%up_i32 = call i32 @llvm.nvvm.shfl.up.i32(i32 %in_i32, i32 1, i32 2)
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store i32 %up_i32, i32* %out_i32
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; CHECK: shfl.up.b32 %f{{[0-9]+}}, %f{{[0-9]+}}, 3, 4;
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%up_float = call float @llvm.nvvm.shfl.up.f32(float %in_float, i32 3, i32 4)
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store float %up_float, float* %out_float
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; CHECK: shfl.bfly.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 5, 6;
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%bfly_i32 = call i32 @llvm.nvvm.shfl.bfly.i32(i32 %in_i32, i32 5, i32 6)
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store i32 %bfly_i32, i32* %out_i32
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; CHECK: shfl.bfly.b32 %f{{[0-9]+}}, %f{{[0-9]+}}, 7, 8;
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%bfly_float = call float @llvm.nvvm.shfl.bfly.f32(float %in_float, i32 7, i32 8)
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store float %bfly_float, float* %out_float
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; CHECK: shfl.idx.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 9, 10;
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%idx_i32 = call i32 @llvm.nvvm.shfl.idx.i32(i32 %in_i32, i32 9, i32 10)
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store i32 %idx_i32, i32* %out_i32
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; CHECK: shfl.idx.b32 %f{{[0-9]+}}, %f{{[0-9]+}}, 11, 12;
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%idx_float = call float @llvm.nvvm.shfl.idx.f32(float %in_float, i32 11, i32 12)
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store float %idx_float, float* %out_float
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ret void
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}
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