Saleem Abdulrasool 367ba1e8b7 ExecutionEngine: fix a bug in the movt/movw relocator ... According to the arm arm specifications, 4 bytes are needed for a shift instead of 8, this was causing the movt instruction to write to a different register sometimes. Patch by Walter Erquinigo! llvm-svn: 280005		2016-08-29 20:42:03 +00:00
..
Interpreter
MCJIT	[RuntimeDyld] Revert r279182 and 279201 -- they broke some ARM bots.	2016-08-19 17:06:39 +00:00
OrcLazy	[ORC] Re-apply r277896, removing bogus triples and datalayouts that broke tests	2016-08-06 22:36:26 +00:00
OrcMCJIT	[RuntimeDyld] Revert r279182 and 279201 -- they broke some ARM bots.	2016-08-19 17:06:39 +00:00
RuntimeDyld	ExecutionEngine: fix a bug in the movt/movw relocator	2016-08-29 20:42:03 +00:00
2010-01-15-UndefValue.ll
fma3-jit.ll	[opaque pointer type] Add textual IR support for explicit type parameter to the call instruction	2015-04-16 23:24:18 +00:00
frem.ll	[opaque pointer type] Add textual IR support for explicit type parameter to the call instruction	2015-04-16 23:24:18 +00:00
lit.local.cfg	[SPARC] Disable unsupported ExecutionEngine tests, and XFAIL a couple	2015-08-07 23:01:16 +00:00
mov64zext32.ll
test-interp-vec-arithm_float.ll
test-interp-vec-arithm_int.ll
test-interp-vec-cast.ll
test-interp-vec-insertelement.ll
test-interp-vec-insertextractvalue.ll
test-interp-vec-loadstore.ll	[opaque pointer type] Add textual IR support for explicit type parameter to the call instruction	2015-04-16 23:24:18 +00:00
test-interp-vec-logical.ll
test-interp-vec-select.ll
test-interp-vec-setcond-fp.ll
test-interp-vec-setcond-int.ll
test-interp-vec-shift.ll
test-interp-vec-shuffle.ll