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342e72a308
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
273 lines
12 KiB
LLVM
273 lines
12 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -check-prefix=SI %s
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@lds = addrspace(3) global [512 x float] undef, align 4
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@lds.f64 = addrspace(3) global [512 x double] undef, align 8
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; SI-LABEL: @simple_read2st64_f32_0_1
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; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:0 offset1:1
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; SI: s_waitcnt lgkmcnt(0)
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; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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define void @simple_read2st64_f32_0_1(float addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
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%val0 = load float addrspace(3)* %arrayidx0, align 4
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%add.x = add nsw i32 %x.i, 64
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%arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
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%val1 = load float addrspace(3)* %arrayidx1, align 4
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%sum = fadd float %val0, %val1
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%out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
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store float %sum, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; SI-LABEL: @simple_read2st64_f32_1_2
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; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:2
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; SI: s_waitcnt lgkmcnt(0)
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; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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define void @simple_read2st64_f32_1_2(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%add.x.0 = add nsw i32 %x.i, 64
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%arrayidx0 = getelementptr inbounds float addrspace(3)* %lds, i32 %add.x.0
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%val0 = load float addrspace(3)* %arrayidx0, align 4
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%add.x.1 = add nsw i32 %x.i, 128
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%arrayidx1 = getelementptr inbounds float addrspace(3)* %lds, i32 %add.x.1
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%val1 = load float addrspace(3)* %arrayidx1, align 4
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%sum = fadd float %val0, %val1
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%out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
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store float %sum, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; SI-LABEL: @simple_read2st64_f32_max_offset
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; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:255
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; SI: s_waitcnt lgkmcnt(0)
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; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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define void @simple_read2st64_f32_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%add.x.0 = add nsw i32 %x.i, 64
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%arrayidx0 = getelementptr inbounds float addrspace(3)* %lds, i32 %add.x.0
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%val0 = load float addrspace(3)* %arrayidx0, align 4
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%add.x.1 = add nsw i32 %x.i, 16320
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%arrayidx1 = getelementptr inbounds float addrspace(3)* %lds, i32 %add.x.1
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%val1 = load float addrspace(3)* %arrayidx1, align 4
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%sum = fadd float %val0, %val1
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%out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
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store float %sum, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; SI-LABEL: @simple_read2st64_f32_over_max_offset
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; SI-NOT: ds_read2st64_b32
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; SI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:256
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; SI: v_add_i32_e32 [[BIGADD:v[0-9]+]], 0x10000, {{v[0-9]+}}
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; SI: ds_read_b32 {{v[0-9]+}}, [[BIGADD]]
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; SI: s_endpgm
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define void @simple_read2st64_f32_over_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%add.x.0 = add nsw i32 %x.i, 64
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%arrayidx0 = getelementptr inbounds float addrspace(3)* %lds, i32 %add.x.0
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%val0 = load float addrspace(3)* %arrayidx0, align 4
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%add.x.1 = add nsw i32 %x.i, 16384
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%arrayidx1 = getelementptr inbounds float addrspace(3)* %lds, i32 %add.x.1
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%val1 = load float addrspace(3)* %arrayidx1, align 4
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%sum = fadd float %val0, %val1
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%out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
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store float %sum, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; SI-LABEL: @odd_invalid_read2st64_f32_0
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; SI-NOT: ds_read2st64_b32
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; SI: s_endpgm
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define void @odd_invalid_read2st64_f32_0(float addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
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%val0 = load float addrspace(3)* %arrayidx0, align 4
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%add.x = add nsw i32 %x.i, 63
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%arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
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%val1 = load float addrspace(3)* %arrayidx1, align 4
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%sum = fadd float %val0, %val1
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%out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
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store float %sum, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; SI-LABEL: @odd_invalid_read2st64_f32_1
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; SI-NOT: ds_read2st64_b32
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; SI: s_endpgm
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define void @odd_invalid_read2st64_f32_1(float addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%add.x.0 = add nsw i32 %x.i, 64
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%arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.0
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%val0 = load float addrspace(3)* %arrayidx0, align 4
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%add.x.1 = add nsw i32 %x.i, 127
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%arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.1
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%val1 = load float addrspace(3)* %arrayidx1, align 4
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%sum = fadd float %val0, %val1
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%out.gep = getelementptr inbounds float addrspace(1)* %out, i32 %x.i
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store float %sum, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; SI-LABEL: @simple_read2st64_f64_0_1
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; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:0 offset1:1
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; SI: s_waitcnt lgkmcnt(0)
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; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}}
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; SI: buffer_store_dwordx2 [[RESULT]]
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; SI: s_endpgm
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define void @simple_read2st64_f64_0_1(double addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
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%val0 = load double addrspace(3)* %arrayidx0, align 8
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%add.x = add nsw i32 %x.i, 64
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%arrayidx1 = getelementptr inbounds [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
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%val1 = load double addrspace(3)* %arrayidx1, align 8
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%sum = fadd double %val0, %val1
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%out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
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store double %sum, double addrspace(1)* %out.gep, align 8
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ret void
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}
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; SI-LABEL: @simple_read2st64_f64_1_2
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; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:2
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; SI: s_waitcnt lgkmcnt(0)
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; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}}
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; SI: buffer_store_dwordx2 [[RESULT]]
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; SI: s_endpgm
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define void @simple_read2st64_f64_1_2(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%add.x.0 = add nsw i32 %x.i, 64
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%arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.0
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%val0 = load double addrspace(3)* %arrayidx0, align 8
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%add.x.1 = add nsw i32 %x.i, 128
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%arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.1
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%val1 = load double addrspace(3)* %arrayidx1, align 8
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%sum = fadd double %val0, %val1
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%out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
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store double %sum, double addrspace(1)* %out.gep, align 8
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ret void
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}
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; Alignment only
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; SI-LABEL: @misaligned_read2st64_f64
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; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:0 offset1:1
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; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:128 offset1:129
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; SI: s_endpgm
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define void @misaligned_read2st64_f64(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %x.i
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%val0 = load double addrspace(3)* %arrayidx0, align 4
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%add.x = add nsw i32 %x.i, 64
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%arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x
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%val1 = load double addrspace(3)* %arrayidx1, align 4
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%sum = fadd double %val0, %val1
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%out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
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store double %sum, double addrspace(1)* %out.gep, align 4
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ret void
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}
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; The maximum is not the usual 0xff because 0xff * 8 * 64 > 0xffff
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; SI-LABEL: @simple_read2st64_f64_max_offset
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; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:4 offset1:127
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; SI: s_waitcnt lgkmcnt(0)
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; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}}
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; SI: buffer_store_dwordx2 [[RESULT]]
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; SI: s_endpgm
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define void @simple_read2st64_f64_max_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%add.x.0 = add nsw i32 %x.i, 256
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%arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.0
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%val0 = load double addrspace(3)* %arrayidx0, align 8
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%add.x.1 = add nsw i32 %x.i, 8128
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%arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.1
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%val1 = load double addrspace(3)* %arrayidx1, align 8
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%sum = fadd double %val0, %val1
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%out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
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store double %sum, double addrspace(1)* %out.gep, align 8
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ret void
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}
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; SI-LABEL: @simple_read2st64_f64_over_max_offset
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; SI-NOT: ds_read2st64_b64
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; SI: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset:512
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; SI: v_add_i32_e32 [[BIGADD:v[0-9]+]], 0x10000, {{v[0-9]+}}
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; SI: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, [[BIGADD]]
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; SI: s_endpgm
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define void @simple_read2st64_f64_over_max_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%add.x.0 = add nsw i32 %x.i, 64
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%arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.0
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%val0 = load double addrspace(3)* %arrayidx0, align 8
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%add.x.1 = add nsw i32 %x.i, 8192
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%arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.1
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%val1 = load double addrspace(3)* %arrayidx1, align 8
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%sum = fadd double %val0, %val1
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%out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
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store double %sum, double addrspace(1)* %out.gep, align 8
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ret void
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}
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; SI-LABEL: @invalid_read2st64_f64_odd_offset
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; SI-NOT: ds_read2st64_b64
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; SI: s_endpgm
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define void @invalid_read2st64_f64_odd_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%add.x.0 = add nsw i32 %x.i, 64
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%arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.0
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%val0 = load double addrspace(3)* %arrayidx0, align 8
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%add.x.1 = add nsw i32 %x.i, 8129
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%arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.1
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%val1 = load double addrspace(3)* %arrayidx1, align 8
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%sum = fadd double %val0, %val1
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%out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
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store double %sum, double addrspace(1)* %out.gep, align 8
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ret void
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}
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; The stride of 8 elements is 8 * 8 bytes. We need to make sure the
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; stride in elements, not bytes, is a multiple of 64.
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; SI-LABEL: @byte_size_only_divisible_64_read2_f64
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; SI-NOT: ds_read2st_b64
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; SI: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:0 offset1:8
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; SI: s_endpgm
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define void @byte_size_only_divisible_64_read2_f64(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %x.i
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%val0 = load double addrspace(3)* %arrayidx0, align 8
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%add.x = add nsw i32 %x.i, 8
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%arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x
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%val1 = load double addrspace(3)* %arrayidx1, align 8
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%sum = fadd double %val0, %val1
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%out.gep = getelementptr inbounds double addrspace(1)* %out, i32 %x.i
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store double %sum, double addrspace(1)* %out.gep, align 4
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.r600.read.tgid.x() #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.r600.read.tgid.y() #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.r600.read.tidig.x() #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.r600.read.tidig.y() #1
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; Function Attrs: noduplicate nounwind
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declare void @llvm.AMDGPU.barrier.local() #2
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { noduplicate nounwind }
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