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342e72a308
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
74 lines
2.6 KiB
LLVM
74 lines
2.6 KiB
LLVM
; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s
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; CHECK-LABEL: {{^}}flt_f64:
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; CHECK: v_cmp_nge_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
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define void @flt_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) {
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%r0 = load double addrspace(1)* %in1
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%r1 = load double addrspace(1)* %in2
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%r2 = fcmp ult double %r0, %r1
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%r3 = zext i1 %r2 to i32
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store i32 %r3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}fle_f64:
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; CHECK: v_cmp_ngt_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
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define void @fle_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) {
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%r0 = load double addrspace(1)* %in1
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%r1 = load double addrspace(1)* %in2
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%r2 = fcmp ule double %r0, %r1
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%r3 = zext i1 %r2 to i32
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store i32 %r3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}fgt_f64:
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; CHECK: v_cmp_nle_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
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define void @fgt_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) {
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%r0 = load double addrspace(1)* %in1
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%r1 = load double addrspace(1)* %in2
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%r2 = fcmp ugt double %r0, %r1
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%r3 = zext i1 %r2 to i32
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store i32 %r3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}fge_f64:
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; CHECK: v_cmp_nlt_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
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define void @fge_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) {
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%r0 = load double addrspace(1)* %in1
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%r1 = load double addrspace(1)* %in2
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%r2 = fcmp uge double %r0, %r1
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%r3 = zext i1 %r2 to i32
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store i32 %r3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}fne_f64:
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; CHECK: v_cmp_neq_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
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define void @fne_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) {
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%r0 = load double addrspace(1)* %in1
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%r1 = load double addrspace(1)* %in2
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%r2 = fcmp une double %r0, %r1
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%r3 = select i1 %r2, double %r0, double %r1
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store double %r3, double addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}feq_f64:
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; CHECK: v_cmp_nlg_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
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define void @feq_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) {
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%r0 = load double addrspace(1)* %in1
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%r1 = load double addrspace(1)* %in2
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%r2 = fcmp ueq double %r0, %r1
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%r3 = select i1 %r2, double %r0, double %r1
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store double %r3, double addrspace(1)* %out
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ret void
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}
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