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https://github.com/RPCS3/llvm-mirror.git
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342e72a308
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
183 lines
6.4 KiB
LLVM
183 lines
6.4 KiB
LLVM
; RUN: llc -O0 -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca < %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-NO-PROMOTE %s
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; RUN: llc -O0 -march=amdgcn -mcpu=bonaire -mattr=+promote-alloca < %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-PROMOTE %s
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; Disable optimizations in case there are optimizations added that
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; specialize away generic pointer accesses.
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; CHECK-LABEL: {{^}}branch_use_flat_i32:
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; CHECK: flat_store_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, [M0, FLAT_SCRATCH]
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; CHECK: s_endpgm
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define void @branch_use_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %gptr, i32 addrspace(3)* %lptr, i32 %x, i32 %c) #0 {
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entry:
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%cmp = icmp ne i32 %c, 0
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br i1 %cmp, label %local, label %global
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local:
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%flat_local = addrspacecast i32 addrspace(3)* %lptr to i32 addrspace(4)*
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br label %end
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global:
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%flat_global = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)*
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br label %end
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end:
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%fptr = phi i32 addrspace(4)* [ %flat_local, %local ], [ %flat_global, %global ]
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store i32 %x, i32 addrspace(4)* %fptr, align 4
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; %val = load i32 addrspace(4)* %fptr, align 4
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; store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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; These testcases might become useless when there are optimizations to
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; remove generic pointers.
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; CHECK-LABEL: {{^}}store_flat_i32:
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; CHECK: v_mov_b32_e32 v[[DATA:[0-9]+]], {{s[0-9]+}}
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; CHECK: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], {{s[0-9]+}}
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; CHECK: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], {{s[0-9]+}}
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; CHECK: flat_store_dword v[[DATA]], v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
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define void @store_flat_i32(i32 addrspace(1)* %gptr, i32 %x) #0 {
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%fptr = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)*
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store i32 %x, i32 addrspace(4)* %fptr, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}store_flat_i64:
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; CHECK: flat_store_dwordx2
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define void @store_flat_i64(i64 addrspace(1)* %gptr, i64 %x) #0 {
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%fptr = addrspacecast i64 addrspace(1)* %gptr to i64 addrspace(4)*
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store i64 %x, i64 addrspace(4)* %fptr, align 8
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ret void
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}
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; CHECK-LABEL: {{^}}store_flat_v4i32:
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; CHECK: flat_store_dwordx4
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define void @store_flat_v4i32(<4 x i32> addrspace(1)* %gptr, <4 x i32> %x) #0 {
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%fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32> addrspace(4)*
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store <4 x i32> %x, <4 x i32> addrspace(4)* %fptr, align 16
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ret void
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}
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; CHECK-LABEL: {{^}}store_flat_trunc_i16:
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; CHECK: flat_store_short
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define void @store_flat_trunc_i16(i16 addrspace(1)* %gptr, i32 %x) #0 {
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%fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)*
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%y = trunc i32 %x to i16
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store i16 %y, i16 addrspace(4)* %fptr, align 2
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ret void
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}
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; CHECK-LABEL: {{^}}store_flat_trunc_i8:
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; CHECK: flat_store_byte
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define void @store_flat_trunc_i8(i8 addrspace(1)* %gptr, i32 %x) #0 {
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%fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)*
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%y = trunc i32 %x to i8
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store i8 %y, i8 addrspace(4)* %fptr, align 2
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ret void
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}
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; CHECK-LABEL @load_flat_i32:
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; CHECK: flat_load_dword
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define void @load_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %gptr) #0 {
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%fptr = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)*
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%fload = load i32 addrspace(4)* %fptr, align 4
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store i32 %fload, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL @load_flat_i64:
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; CHECK: flat_load_dwordx2
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define void @load_flat_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %gptr) #0 {
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%fptr = addrspacecast i64 addrspace(1)* %gptr to i64 addrspace(4)*
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%fload = load i64 addrspace(4)* %fptr, align 4
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store i64 %fload, i64 addrspace(1)* %out, align 8
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ret void
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}
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; CHECK-LABEL @load_flat_v4i32:
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; CHECK: flat_load_dwordx4
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define void @load_flat_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %gptr) #0 {
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%fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32> addrspace(4)*
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%fload = load <4 x i32> addrspace(4)* %fptr, align 4
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store <4 x i32> %fload, <4 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; CHECK-LABEL @sextload_flat_i8:
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; CHECK: flat_load_sbyte
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define void @sextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 {
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%fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)*
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%fload = load i8 addrspace(4)* %fptr, align 4
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%ext = sext i8 %fload to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL @zextload_flat_i8:
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; CHECK: flat_load_ubyte
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define void @zextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 {
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%fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)*
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%fload = load i8 addrspace(4)* %fptr, align 4
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%ext = zext i8 %fload to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL @sextload_flat_i16:
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; CHECK: flat_load_sshort
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define void @sextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 {
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%fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)*
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%fload = load i16 addrspace(4)* %fptr, align 4
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%ext = sext i16 %fload to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL @zextload_flat_i16:
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; CHECK: flat_load_ushort
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define void @zextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 {
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%fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)*
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%fload = load i16 addrspace(4)* %fptr, align 4
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%ext = zext i16 %fload to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; TODO: This should not be zero when registers are used for small
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; scratch allocations again.
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; Check for prologue initializing special SGPRs pointing to scratch.
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; CHECK-LABEL: {{^}}store_flat_scratch:
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; CHECK: s_movk_i32 flat_scratch_lo, 0
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; CHECK-NO-PROMOTE: s_movk_i32 flat_scratch_hi, 0x28{{$}}
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; CHECK-PROMOTE: s_movk_i32 flat_scratch_hi, 0x0{{$}}
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; CHECK: flat_store_dword
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; CHECK: s_barrier
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; CHECK: flat_load_dword
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define void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 {
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%alloca = alloca i32, i32 9, align 4
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%x = call i32 @llvm.r600.read.tidig.x() #3
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%pptr = getelementptr i32* %alloca, i32 %x
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%fptr = addrspacecast i32* %pptr to i32 addrspace(4)*
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store i32 %x, i32 addrspace(4)* %fptr
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; Dummy call
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call void @llvm.AMDGPU.barrier.local() #1
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%reload = load i32 addrspace(4)* %fptr, align 4
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store i32 %reload, i32 addrspace(1)* %out, align 4
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ret void
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}
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declare void @llvm.AMDGPU.barrier.local() #1
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declare i32 @llvm.r600.read.tidig.x() #3
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attributes #0 = { nounwind }
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attributes #1 = { nounwind noduplicate }
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attributes #3 = { nounwind readnone }
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