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342e72a308
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
29 lines
1.2 KiB
LLVM
29 lines
1.2 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone
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declare double @llvm.convert.from.fp16.f64(i16) nounwind readnone
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; SI-LABEL: {{^}}test_convert_fp16_to_fp32:
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; SI: buffer_load_ushort [[VAL:v[0-9]+]]
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; SI: v_cvt_f32_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
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; SI: buffer_store_dword [[RESULT]]
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define void @test_convert_fp16_to_fp32(float addrspace(1)* noalias %out, i16 addrspace(1)* noalias %in) nounwind {
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%val = load i16 addrspace(1)* %in, align 2
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%cvt = call float @llvm.convert.from.fp16.f32(i16 %val) nounwind readnone
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_convert_fp16_to_fp64:
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; SI: buffer_load_ushort [[VAL:v[0-9]+]]
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; SI: v_cvt_f32_f16_e32 [[RESULT32:v[0-9]+]], [[VAL]]
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; SI: v_cvt_f64_f32_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[RESULT32]]
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; SI: buffer_store_dwordx2 [[RESULT]]
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define void @test_convert_fp16_to_fp64(double addrspace(1)* noalias %out, i16 addrspace(1)* noalias %in) nounwind {
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%val = load i16 addrspace(1)* %in, align 2
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%cvt = call double @llvm.convert.from.fp16.f64(i16 %val) nounwind readnone
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store double %cvt, double addrspace(1)* %out, align 4
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ret void
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}
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