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llvm-mirror/test/MC/ARM/directive-arch_extension-fp.s
Oliver Stannard dacbc9891d [ARM] Use new assembler diags for ARM 
This converts the ARM AsmParser to use the new assembly matcher error
reporting mechanism, which allows errors to be reported for multiple
instruction encodings when it is ambiguous which one the user intended
to use.

By itself this doesn't improve many error messages, because we don't have
diagnostic text for most operand types, but as we add that then this will allow
more of those diagnostic strings to be used when they are relevant.

Differential revision: https://reviews.llvm.org/D31530

llvm-svn: 314779
2017-10-03 10:26:11 +00:00

284 lines
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ArmAsm
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@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \
@ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK
@ RUN: not llvm-mc -triple armv8-eabi -filetype asm -o /dev/null 2>&1 %s \
@ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK
@ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \
@ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK
@ RUN: not llvm-mc -triple thumbv8-eabi -filetype asm -o /dev/null 2>&1 %s \
@ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK
.syntax unified
.arch_extension fp
@ CHECK-V7: error: architectural extension 'fp' is not allowed for the current base architecture
@ CHECK-V7-NEXT: .arch_extension fp
@ CHECK-V7-NEXT: ^
.type fp,%function
fp:
vmrs r0, mvfr2
@ CHECK-V7: instruction requires: FPARMv8
vselgt.f32 s0, s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vselge.f32 s0, s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vseleq.f32 s0, s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vselvs.f32 s0, s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vmaxnm.f32 s0, s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vminnm.f32 s0, s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vselgt.f64 d0, d0, d0
@ CHECK-V7: instruction requires: FPARMv8
vselge.f64 d0, d0, d0
@ CHECK-V7: instruction requires: FPARMv8
vseleq.f64 d0, d0, d0
@ CHECK-V7: instruction requires: FPARMv8
vselvs.f64 d0, d0, d0
@ CHECK-V7: instruction requires: FPARMv8
vmaxnm.f64 d0, d0, d0
@ CHECK-V7: instruction requires: FPARMv8
vminnm.f64 d0, d0, d0
@ CHECK-V7: instruction requires: FPARMv8
vcvtb.f64.f16 d0, s0
@ CHECK-V7: instruction requires: FPARMv8
vcvtb.f16.f64 s0, d0
@ CHECK-V7: instruction requires: FPARMv8
vcvtt.f64.f16 d0, s0
@ CHECK-V7: instruction requires: FPARMv8
vcvtt.f16.f64 s0, d0
@ CHECK-V7: instruction requires: FPARMv8
vcvta.s32.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vcvta.u32.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vcvta.s32.f64 s0, d0
@ CHECK-V7: instruction requires: FPARMv8
vcvta.u32.f64 s0, d0
@ CHECK-V7: instruction requires: FPARMv8
vcvtn.s32.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vcvtn.u32.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vcvtn.s32.f64 s0, d0
@ CHECK-V7: instruction requires: FPARMv8
vcvtn.u32.f64 s0, d0
@ CHECK-V7: instruction requires: FPARMv8
vcvtp.s32.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vcvtp.u32.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vcvtp.s32.f64 s0, d0
@ CHECK-V7: instruction requires: FPARMv8
vcvtp.u32.f64 s0, d0
@ CHECK-V7: instruction requires: FPARMv8
vcvtm.s32.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vcvtm.u32.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vcvtm.s32.f64 s0, d0
@ CHECK-V7: instruction requires: FPARMv8
vcvtm.u32.f64 s0, d0
@ CHECK-V7: instruction requires: FPARMv8
vrintz.f32 s0, s1
@ CHECK-V7: instruction requires: FPARMv8
vrintz.f64 d0, d1
@ CHECK-V7: instruction requires: FPARMv8
vrintz.f32.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vrintz.f64.f64 d0, d0
@ CHECK-V7: instruction requires: FPARMv8
vrintr.f32 s0, s1
@ CHECK-V7: instruction requires: FPARMv8
vrintr.f64 d0, d1
@ CHECK-V7: instruction requires: FPARMv8
vrintr.f32.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vrintr.f64.f64 d0, d0
@ CHECK-V7: instruction requires: FPARMv8
vrintx.f32 s0, s1
@ CHECK-V7: instruction requires: FPARMv8
vrintx.f64 d0, d1
@ CHECK-V7: instruction requires: FPARMv8
vrintx.f32.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vrintx.f64.f64 d0, d0
@ CHECK-V7: instruction requires: FPARMv8
vrinta.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vrinta.f64 d0, d0
@ CHECK-V7: instruction requires: FPARMv8
vrinta.f32.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vrinta.f64.f64 d0, d0
@ CHECK-V7: instruction requires: FPARMv8
vrintn.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vrintn.f64 d0, d0
@ CHECK-V7: instruction requires: FPARMv8
vrintn.f32.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vrintn.f64.f64 d0, d0
@ CHECK-V7: instruction requires: FPARMv8
vrintp.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vrintp.f64 d0, d0
@ CHECK-V7: instruction requires: FPARMv8
vrintp.f32.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vrintp.f64.f64 d0, d0
@ CHECK-V7: instruction requires: FPARMv8
vrintm.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vrintm.f64 d0, d0
@ CHECK-V7: instruction requires: FPARMv8
vrintm.f32.f32 s0, s0
@ CHECK-V7: instruction requires: FPARMv8
vrintm.f64.f64 d0, d0
@ CHECK-V7: instruction requires: FPARMv8
.arch_extension nofp
@ CHECK-V7: error: architectural extension 'fp' is not allowed for the current base architecture
@ CHECK-V7-NEXT: .arch_extension nofp
@ CHECK-V7-NEXT: ^
.type nofp,%function
nofp:
vmrs r0, mvfr2
@ CHECK: instruction requires: FPARMv8
vselgt.f32 s0, s0, s0
@ CHECK: instruction requires: FPARMv8
vselge.f32 s0, s0, s0
@ CHECK: instruction requires: FPARMv8
vseleq.f32 s0, s0, s0
@ CHECK: instruction requires: FPARMv8
vselvs.f32 s0, s0, s0
@ CHECK: instruction requires: FPARMv8
vmaxnm.f32 s0, s0, s0
@ CHECK: instruction requires: FPARMv8
vminnm.f32 s0, s0, s0
@ CHECK: instruction requires: FPARMv8
vselgt.f64 d0, d0, d0
@ CHECK: instruction requires: FPARMv8
vselge.f64 d0, d0, d0
@ CHECK: instruction requires: FPARMv8
vseleq.f64 d0, d0, d0
@ CHECK: instruction requires: FPARMv8
vselvs.f64 d0, d0, d0
@ CHECK: instruction requires: FPARMv8
vmaxnm.f64 d0, d0, d0
@ CHECK: instruction requires: FPARMv8
vminnm.f64 d0, d0, d0
@ CHECK: instruction requires: FPARMv8
vcvtb.f64.f16 d0, s0
@ CHECK: instruction requires: FPARMv8
vcvtb.f16.f64 s0, d0
@ CHECK: instruction requires: FPARMv8
vcvtt.f64.f16 d0, s0
@ CHECK: instruction requires: FPARMv8
vcvtt.f16.f64 s0, d0
@ CHECK: instruction requires: FPARMv8
vcvta.s32.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vcvta.u32.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vcvta.s32.f64 s0, d0
@ CHECK: instruction requires: FPARMv8
vcvta.u32.f64 s0, d0
@ CHECK: instruction requires: FPARMv8
vcvtn.s32.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vcvtn.u32.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vcvtn.s32.f64 s0, d0
@ CHECK: instruction requires: FPARMv8
vcvtn.u32.f64 s0, d0
@ CHECK: instruction requires: FPARMv8
vcvtp.s32.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vcvtp.u32.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vcvtp.s32.f64 s0, d0
@ CHECK: instruction requires: FPARMv8
vcvtp.u32.f64 s0, d0
@ CHECK: instruction requires: FPARMv8
vcvtm.s32.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vcvtm.u32.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vcvtm.s32.f64 s0, d0
@ CHECK: instruction requires: FPARMv8
vcvtm.u32.f64 s0, d0
@ CHECK: instruction requires: FPARMv8
vrintz.f32 s0, s1
@ CHECK: instruction requires: FPARMv8
vrintz.f64 d0, d1
@ CHECK: instruction requires: FPARMv8
vrintz.f32.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vrintz.f64.f64 d0, d0
@ CHECK: instruction requires: FPARMv8
vrintr.f32 s0, s1
@ CHECK: instruction requires: FPARMv8
vrintr.f64 d0, d1
@ CHECK: instruction requires: FPARMv8
vrintr.f32.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vrintr.f64.f64 d0, d0
@ CHECK: instruction requires: FPARMv8
vrintx.f32 s0, s1
@ CHECK: instruction requires: FPARMv8
vrintx.f64 d0, d1
@ CHECK: instruction requires: FPARMv8
vrintx.f32.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vrintx.f64.f64 d0, d0
@ CHECK: instruction requires: FPARMv8
vrinta.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vrinta.f64 d0, d0
@ CHECK: instruction requires: FPARMv8
vrinta.f32.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vrinta.f64.f64 d0, d0
@ CHECK: instruction requires: FPARMv8
vrintn.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vrintn.f64 d0, d0
@ CHECK: instruction requires: FPARMv8
vrintn.f32.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vrintn.f64.f64 d0, d0
@ CHECK: instruction requires: FPARMv8
vrintp.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vrintp.f64 d0, d0
@ CHECK: instruction requires: FPARMv8
vrintp.f32.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vrintp.f64.f64 d0, d0
@ CHECK: instruction requires: FPARMv8
vrintm.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vrintm.f64 d0, d0
@ CHECK: instruction requires: FPARMv8
vrintm.f32.f32 s0, s0
@ CHECK: instruction requires: FPARMv8
vrintm.f64.f64 d0, d0
@ CHECK: instruction requires: FPARMv8
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