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3d936b9a18
This adds diagnostic strings for the ARM general-purpose register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, rGPR, requires C++ code to select the correct error message, as that class contains different registers in pre-v8 and v8 targets. The rest can all have their diagnostic strings stored in the tablegen description of them. Differential revision: https://reviews.llvm.org/D36692 llvm-svn: 315303
35 lines
1.4 KiB
ArmAsm
35 lines
1.4 KiB
ArmAsm
# RUN: not llvm-mc -triple thumbv7 -mcpu=cortex-m0 %s 2>&1 | FileCheck %s
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.thumb
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ADDs r1, r0, #0xFFFFFFF5
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# CHECK: error: invalid instruction, any one of the following would fix this:
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# CHECK-DAG: note: instruction requires: thumb2
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# CHECK-DAG: note: invalid operand for instruction
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# CHECK-DAG: note: operand must be an immediate in the range [0,7]
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# CHECK-DAG: note: operand must be a register in range [r0, r7]
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ADDs r0, #0xFFFFFEFF
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# CHECK: error: invalid instruction, any one of the following would fix this:
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# CHECK-DAG: note: invalid operand for instruction
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# CHECK-DAG: note: operand must be an immediate in the range [0,255]
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SUBs r1, r0, #0xFFFFFFF5
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# CHECK: error: invalid instruction, any one of the following would fix this:
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# CHECK-DAG: note: invalid operand for instruction
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# CHECK-DAG: note: operand must be an immediate in the range [0,7]
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# CHECK-DAG: note: operand must be a register in range [r0, r7]
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SUBs r0, #0xFFFFFEFF
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# CHECK: error: invalid instruction, any one of the following would fix this:
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# CHECK-DAG: note: invalid operand for instruction
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# CHECK-DAG: note: operand must be an immediate in the range [0,255]
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ORRs r0, r1, #0xFFFFFF00
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# CHECK: error: invalid instruction, any one of the following would fix this:
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# CHECK-DAG: note: instruction requires: thumb2
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# CHECK-DAG: note: too many operands for instruction
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ORNs r0, r1, #0xFFFFFF00
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# CHECK: error: instruction requires: thumb2
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