mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 19:23:23 +01:00
45b647d5eb
This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. llvm-svn: 317647
99 lines
3.5 KiB
C++
99 lines
3.5 KiB
C++
//===-- MSP430InstrInfo.h - MSP430 Instruction Information ------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the MSP430 implementation of the TargetInstrInfo class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
|
|
#define LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
|
|
|
|
#include "MSP430RegisterInfo.h"
|
|
#include "llvm/CodeGen/TargetInstrInfo.h"
|
|
|
|
#define GET_INSTRINFO_HEADER
|
|
#include "MSP430GenInstrInfo.inc"
|
|
|
|
namespace llvm {
|
|
|
|
class MSP430Subtarget;
|
|
|
|
/// MSP430II - This namespace holds all of the target specific flags that
|
|
/// instruction info tracks.
|
|
///
|
|
namespace MSP430II {
|
|
enum {
|
|
SizeShift = 2,
|
|
SizeMask = 7 << SizeShift,
|
|
|
|
SizeUnknown = 0 << SizeShift,
|
|
SizeSpecial = 1 << SizeShift,
|
|
Size2Bytes = 2 << SizeShift,
|
|
Size4Bytes = 3 << SizeShift,
|
|
Size6Bytes = 4 << SizeShift
|
|
};
|
|
}
|
|
|
|
class MSP430InstrInfo : public MSP430GenInstrInfo {
|
|
const MSP430RegisterInfo RI;
|
|
virtual void anchor();
|
|
public:
|
|
explicit MSP430InstrInfo(MSP430Subtarget &STI);
|
|
|
|
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
|
/// such, whenever a client has an instance of instruction info, it should
|
|
/// always be able to get register info as well (through this method).
|
|
///
|
|
const TargetRegisterInfo &getRegisterInfo() const { return RI; }
|
|
|
|
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
|
|
bool KillSrc) const override;
|
|
|
|
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned SrcReg, bool isKill,
|
|
int FrameIndex,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI) const override;
|
|
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned DestReg, int FrameIdx,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI) const override;
|
|
|
|
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
|
|
|
|
// Branch folding goodness
|
|
bool
|
|
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|
|
bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
|
|
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
|
MachineBasicBlock *&FBB,
|
|
SmallVectorImpl<MachineOperand> &Cond,
|
|
bool AllowModify) const override;
|
|
|
|
unsigned removeBranch(MachineBasicBlock &MBB,
|
|
int *BytesRemoved = nullptr) const override;
|
|
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
|
const DebugLoc &DL,
|
|
int *BytesAdded = nullptr) const override;
|
|
|
|
int64_t getFramePoppedByCallee(const MachineInstr &I) const {
|
|
assert(isFrameInstr(I) && "Not a frame instruction");
|
|
assert(I.getOperand(1).getImm() >= 0 && "Size must not be negative");
|
|
return I.getOperand(1).getImm();
|
|
}
|
|
};
|
|
|
|
}
|
|
|
|
#endif
|