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ce0f9aef12
The fast register allocator is not supposed to work in the optimizing pipeline. It doesn't make sense to compute live intervals, run full copy coalescing, and then run RAFast. Fast register allocation in the optimizing pipeline is better done by RABasic. llvm-svn: 158242
60 lines
2.8 KiB
LLVM
60 lines
2.8 KiB
LLVM
; RUN: llc -regalloc=fast -optimize-regalloc=0 -verify-machineinstrs < %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin"
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; This test causes a virtual FP register to be redefined while it is live:
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;BB#5: derived from LLVM BB %bb10
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; Predecessors according to CFG: BB#4 BB#5
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; %reg1024<def> = MOV_Fp8080 %reg1034
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; %reg1025<def> = MUL_Fp80m32 %reg1024, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
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; %reg1034<def> = MOV_Fp8080 %reg1025
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; FP_REG_KILL %FP0<imp-def>, %FP1<imp-def>, %FP2<imp-def>, %FP3<imp-def>, %FP4<imp-def>, %FP5<imp-def>, %FP6<imp-def>
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; JMP_4 <BB#5>
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; Successors according to CFG: BB#5
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;
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; The X86FP pass needs good kill flags, like on %FP0 representing %reg1034:
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;BB#5: derived from LLVM BB %bb10
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; Predecessors according to CFG: BB#4 BB#5
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; %FP0<def> = LD_Fp80m <fi#3>, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
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; %FP1<def> = MOV_Fp8080 %FP0<kill>
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; %FP2<def> = MUL_Fp80m32 %FP1, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
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; %FP0<def> = MOV_Fp8080 %FP2
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; ST_FpP80m <fi#3>, 1, %reg0, 0, %reg0, %FP0<kill>; mem:ST10[FixedStack3](align=4)
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; ST_FpP80m <fi#4>, 1, %reg0, 0, %reg0, %FP1<kill>; mem:ST10[FixedStack4](align=4)
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; ST_FpP80m <fi#5>, 1, %reg0, 0, %reg0, %FP2<kill>; mem:ST10[FixedStack5](align=4)
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; FP_REG_KILL %FP0<imp-def>, %FP1<imp-def>, %FP2<imp-def>, %FP3<imp-def>, %FP4<imp-def>, %FP5<imp-def>, %FP6<imp-def>
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; JMP_4 <BB#5>
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; Successors according to CFG: BB#5
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define fastcc i32 @sqlite3AtoF(i8* %z, double* nocapture %pResult) nounwind ssp {
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entry:
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br i1 undef, label %bb2, label %bb1.i.i
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bb1.i.i: ; preds = %entry
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unreachable
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bb2: ; preds = %entry
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br i1 undef, label %isdigit339.exit11.preheader, label %bb13
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isdigit339.exit11.preheader: ; preds = %bb2
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br i1 undef, label %bb12, label %bb10
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bb10: ; preds = %bb10, %isdigit339.exit11.preheader
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%divisor.041 = phi x86_fp80 [ %0, %bb10 ], [ 0xK3FFF8000000000000000, %isdigit339.exit11.preheader ] ; <x86_fp80> [#uses=1]
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%0 = fmul x86_fp80 %divisor.041, 0xK4002A000000000000000 ; <x86_fp80> [#uses=2]
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br i1 false, label %bb12, label %bb10
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bb12: ; preds = %bb10, %isdigit339.exit11.preheader
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%divisor.0.lcssa = phi x86_fp80 [ 0xK3FFF8000000000000000, %isdigit339.exit11.preheader ], [ %0, %bb10 ] ; <x86_fp80> [#uses=0]
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br label %bb13
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bb13: ; preds = %bb12, %bb2
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br i1 undef, label %bb34, label %bb36
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bb34: ; preds = %bb13
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br label %bb36
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bb36: ; preds = %bb34, %bb13
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ret i32 undef
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}
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