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d09b64fc25
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
29 lines
1.2 KiB
LLVM
29 lines
1.2 KiB
LLVM
; RUN: llc < %s -tailcallopt -mcpu=generic -mtriple=x86_64-linux -post-RA-scheduler=true | FileCheck %s
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; RUN: llc < %s -tailcallopt -mcpu=generic -mtriple=x86_64-win32 -post-RA-scheduler=true | FileCheck %s
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; FIXME: Redundant unused stack allocation could be eliminated.
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; CHECK: subq ${{24|72|80}}, %rsp
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; Check that lowered arguments on the stack do not overwrite each other.
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; Add %in1 %p1 to a different temporary register (%eax).
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; CHECK: movl [[A1:32|144]](%rsp), [[R1:%e..]]
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; Move param %in1 to temp register (%r10d).
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; CHECK: movl [[A2:40|152]](%rsp), [[R2:%[a-z0-9]+]]
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; Add %in1 %p1 to a different temporary register (%eax).
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; CHECK: addl {{%edi|%ecx}}, [[R1]]
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; Move param %in2 to stack.
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; CHECK: movl [[R2]], [[A1]](%rsp)
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; Move result of addition to stack.
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; CHECK: movl [[R1]], [[A2]](%rsp)
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; Eventually, do a TAILCALL
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; CHECK: TAILCALL
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declare fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %a, i32 %b) nounwind
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define fastcc i32 @tailcaller(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in1, i32 %in2) nounwind {
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entry:
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%tmp = add i32 %in1, %p1
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%retval = tail call fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in2,i32 %tmp)
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ret i32 %retval
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}
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