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(defined by the x32 ABI) mode, in which case its pointers are 32-bits in size. This knowledge is also added to X86RegisterInfo that now returns the appropriate registers in getPointerRegClass. There are many outcomes to this change. In order to keep the patches separate and manageable, we start by focusing on some simple testable cases. The patch adds a test with passing a pointer to a function - focusing on the difference between the two data models for x86-64. Another test is added for handling of 'sret' arguments (and functionality is added in X86ISelLowering to make it work). A note on naming: the "x32 ABI" document refers to the AMD64 architecture (in LLVM it's distinguished by being is64Bits() in the x86 subtarget) with two variations: the LP64 (default) data model, and the ILP32 data model. This patch adds predicates to the subtarget which are consistent with this naming scheme. llvm-svn: 173503
30 lines
686 B
LLVM
30 lines
686 B
LLVM
; RUN: llc -mtriple=x86_64-pc-linux < %s | FileCheck %s
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; RUN: llc -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s
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; %in is kept in %esi for both ABIs. But the pointer will be passed in %edi
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; for x32, not %rdi
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; CHECK: movl %esi, (%rdi)
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; X32ABI: movl %esi, (%edi)
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define void @foo(i32* nocapture %out, i32 %in) nounwind {
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entry:
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store i32 %in, i32* %out, align 4
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ret void
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}
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; CHECK: bar
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; CHECK: movl (%rsi), %eax
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; Similarly here, but for loading
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; X32ABI: bar
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; X32ABI: movl (%esi), %eax
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define void @bar(i32* nocapture %pOut, i32* nocapture %pIn) nounwind {
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entry:
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%0 = load i32* %pIn, align 4
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store i32 %0, i32* %pOut, align 4
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ret void
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}
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