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Previously, only regular AArch64 instructions were annotated with SchedRW lists. This patch does the same for NEON enabling these instructions to be scheduled by the MIScheduler. Additionally, store operations are now modeled and a few SchedRW lists were updated for bug fixes (e.g. multiple def operands). Reviewers: apazos, mcrosier, atrick Patch by Dave Estes <cestes@codeaurora.org>! llvm-svn: 204505
113 lines
4.3 KiB
LLVM
113 lines
4.3 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
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;
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; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
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; much higher than the ADD instructions in order to hide latency. When not
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; specifying a subtarget, the MADD will remain near the end of the block.
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;
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; CHECK: ********** MI Scheduling **********
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; CHECK: main
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; CHECK: *** Final schedule for BB#2 ***
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; CHECK: SU(13)
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; CHECK: MADDwwww
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; CHECK: SU(4)
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; CHECK: ADDwwi_lsl0_s
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; CHECK: ********** INTERVALS **********
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@main.x = private unnamed_addr constant [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 4
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@main.y = private unnamed_addr constant [8 x i32] [i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2], align 4
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; Function Attrs: nounwind
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define i32 @main() #0 {
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entry:
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%retval = alloca i32, align 4
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%x = alloca [8 x i32], align 4
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%y = alloca [8 x i32], align 4
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%i = alloca i32, align 4
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%xx = alloca i32, align 4
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%yy = alloca i32, align 4
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store i32 0, i32* %retval
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%0 = bitcast [8 x i32]* %x to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast ([8 x i32]* @main.x to i8*), i64 32, i32 4, i1 false)
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%1 = bitcast [8 x i32]* %y to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast ([8 x i32]* @main.y to i8*), i64 32, i32 4, i1 false)
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store i32 0, i32* %xx, align 4
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store i32 0, i32* %yy, align 4
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store i32 0, i32* %i, align 4
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br label %for.cond
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for.cond: ; preds = %for.inc, %entry
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%2 = load i32* %i, align 4
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%cmp = icmp slt i32 %2, 8
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br i1 %cmp, label %for.body, label %for.end
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for.body: ; preds = %for.cond
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%3 = load i32* %i, align 4
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%idxprom = sext i32 %3 to i64
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%arrayidx = getelementptr inbounds [8 x i32]* %x, i32 0, i64 %idxprom
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%4 = load i32* %arrayidx, align 4
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%add = add nsw i32 %4, 1
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store i32 %add, i32* %xx, align 4
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%5 = load i32* %xx, align 4
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%add1 = add nsw i32 %5, 12
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store i32 %add1, i32* %xx, align 4
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%6 = load i32* %xx, align 4
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%add2 = add nsw i32 %6, 23
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store i32 %add2, i32* %xx, align 4
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%7 = load i32* %xx, align 4
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%add3 = add nsw i32 %7, 34
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store i32 %add3, i32* %xx, align 4
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%8 = load i32* %i, align 4
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%idxprom4 = sext i32 %8 to i64
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%arrayidx5 = getelementptr inbounds [8 x i32]* %y, i32 0, i64 %idxprom4
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%9 = load i32* %arrayidx5, align 4
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%10 = load i32* %yy, align 4
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%mul = mul nsw i32 %10, %9
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store i32 %mul, i32* %yy, align 4
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br label %for.inc
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for.inc: ; preds = %for.body
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%11 = load i32* %i, align 4
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%inc = add nsw i32 %11, 1
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store i32 %inc, i32* %i, align 4
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br label %for.cond
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for.end: ; preds = %for.cond
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%12 = load i32* %xx, align 4
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%13 = load i32* %yy, align 4
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%add6 = add nsw i32 %12, %13
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ret i32 %add6
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}
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; The Cortex-A53 machine model will cause the FDIVvvv_42 to be raised to
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; hide latency. Whereas normally there would only be a single FADDvvv_4s
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; after it, this test checks to make sure there are more than one.
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;
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; CHECK: ********** MI Scheduling **********
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; CHECK: neon4xfloat:BB#0
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; CHECK: *** Final schedule for BB#0 ***
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; CHECK: FDIVvvv_4S
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; CHECK: FADDvvv_4S
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; CHECK: FADDvvv_4S
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; CHECK: ********** INTERVALS **********
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define <4 x float> @neon4xfloat(<4 x float> %A, <4 x float> %B) {
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%tmp1 = fadd <4 x float> %A, %B;
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%tmp2 = fadd <4 x float> %A, %tmp1;
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%tmp3 = fadd <4 x float> %A, %tmp2;
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%tmp4 = fadd <4 x float> %A, %tmp3;
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%tmp5 = fadd <4 x float> %A, %tmp4;
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%tmp6 = fadd <4 x float> %A, %tmp5;
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%tmp7 = fadd <4 x float> %A, %tmp6;
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%tmp8 = fadd <4 x float> %A, %tmp7;
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%tmp9 = fdiv <4 x float> %A, %B;
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%tmp10 = fadd <4 x float> %tmp8, %tmp9;
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ret <4 x float> %tmp10
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}
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; Function Attrs: nounwind
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind }
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