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c40d85dda5
This is needed because of the patterns we have for the VP[SLL/SRA/SRL][W/D/Q] instructions. llvm-svn: 160222
32 lines
1.6 KiB
LLVM
32 lines
1.6 KiB
LLVM
; RUN: llc < %s -march=x86 -mcpu=corei7 -mattr=+avx
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; PR13352
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declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>) nounwind readnone
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define void @f_f() nounwind {
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allocas:
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br label %for_loop29
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for_loop29: ; preds = %safe_if_after_true, %allocas
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%indvars.iv596 = phi i64 [ %indvars.iv.next597, %safe_if_after_true ], [ 0, %allocas ]
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%0 = trunc i64 %indvars.iv596 to i32
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%smear.15 = insertelement <16 x i32> undef, i32 %0, i32 15
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%bitop = lshr <16 x i32> zeroinitializer, %smear.15
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%bitop35 = and <16 x i32> %bitop, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%bitop35_to_bool = icmp ne <16 x i32> %bitop35, zeroinitializer
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%val_to_boolvec32 = sext <16 x i1> %bitop35_to_bool to <16 x i32>
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%floatmask.i526 = bitcast <16 x i32> %val_to_boolvec32 to <16 x float>
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%mask1.i529 = shufflevector <16 x float> %floatmask.i526, <16 x float> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%"internal_mask&function_mask41_any" = icmp eq i32 undef, 0
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br i1 %"internal_mask&function_mask41_any", label %safe_if_after_true, label %safe_if_run_true
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safe_if_after_true: ; preds = %for_loop29
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%indvars.iv.next597 = add i64 %indvars.iv596, 1
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br label %for_loop29
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safe_if_run_true: ; preds = %for_loop29
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%blend1.i583 = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> undef, <8 x float> undef, <8 x float> %mask1.i529) nounwind
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unreachable
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}
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