Nate Begeman 85cd65b389 Change codegen for setcc to read the bit directly out of the condition ... register. Added support in the .td file for the g5-specific variant of cr -> gpr moves that executes faster, but we currently don't generate it. llvm-svn: 21314		2005-04-18 02:43:24 +00:00
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Alpha	fix calls	2005-04-14 17:34:20 +00:00
CBackend	Fix the 3 regressions last night, due to my buggy patch from yesterday.	2005-03-19 17:35:11 +00:00
IA64	print negative 64 bit immediates as negative numbers, makes things a little	2005-04-14 10:08:01 +00:00
PowerPC	Change codegen for setcc to read the bit directly out of the condition	2005-04-18 02:43:24 +00:00
Skeleton	ignore generated files	2004-11-21 00:01:54 +00:00
SparcV8	This mega patch converts us from using Function::a{iterator|begin|end} to	2005-03-15 04:54:21 +00:00
SparcV9	Fix CodeGen/SparcV9/2005-05-09-GEP-Crash.ll a crash on some specfp program	2005-04-09 06:27:14 +00:00
X86	Make pattern isel default for ppc	2005-04-15 22:12:16 +00:00
Makefile	build the IA64 target as a .so for now	2005-03-17 18:29:04 +00:00
MRegisterInfo.cpp	Move destructor out of line to avoid vtable emission in every file that includes the header. Thanks to sabre.	2004-10-27 06:00:53 +00:00
Target.td	Add some bits that can be set for instructions.	2005-01-02 02:27:48 +00:00
TargetData.cpp	add a StructLayout::getElementContainingOffset method.	2005-03-13 19:04:41 +00:00
TargetFrameInfo.cpp	Fix compilation errors with VS 2005, patch contributed by Aaron Gray.	2005-02-17 21:40:27 +00:00
TargetInstrInfo.cpp	Finegrainify namespacification	2005-01-19 06:53:34 +00:00
TargetLowering.cpp	Add a hook to find out how the target handles shift amounts that are out of	2005-01-19 03:36:14 +00:00
TargetMachine.cpp	Make pattern isel default for ppc	2005-04-15 22:12:16 +00:00
TargetMachineRegistry.cpp	Implement TargetRegistrationListener	2004-07-11 06:03:21 +00:00
TargetSchedInfo.cpp	Improve compatiblity with HPUX on Itanium, patch by Duraid Madina	2005-01-16 01:31:31 +00:00