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https://github.com/RPCS3/llvm-mirror.git
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a428f4ce70
Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing mode handling. PR19455 and rdar://16650642 llvm-svn: 206495
97 lines
2.9 KiB
LLVM
97 lines
2.9 KiB
LLVM
; RUN: llc -mtriple=arm64-linux-gnu -enable-misched=false < %s | FileCheck %s
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@var = global i32 0, align 4
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define i128 @test_i128_align(i32, i128 %arg, i32 %after) {
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store i32 %after, i32* @var, align 4
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; CHECK: str w4, [{{x[0-9]+}}, :lo12:var]
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ret i128 %arg
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; CHECK: mov x0, x2
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; CHECK: mov x1, x3
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}
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@var64 = global i64 0, align 8
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; Check stack slots are 64-bit at all times.
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define void @test_stack_slots([8 x i32], i1 %bool, i8 %char, i16 %short,
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i32 %int, i64 %long) {
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; Part of last store. Blasted scheduler.
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; CHECK: ldr [[LONG:x[0-9]+]], [sp, #32]
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%ext_bool = zext i1 %bool to i64
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store volatile i64 %ext_bool, i64* @var64, align 8
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; CHECK: ldr w[[EXT:[0-9]+]], [sp]
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; CHECK: and x[[EXTED:[0-9]+]], x[[EXT]], #0x1
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; CHECK: str x[[EXTED]], [{{x[0-9]+}}, :lo12:var64]
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%ext_char = zext i8 %char to i64
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store volatile i64 %ext_char, i64* @var64, align 8
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; CHECK: ldrb w[[EXT:[0-9]+]], [sp, #8]
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; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
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%ext_short = zext i16 %short to i64
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store volatile i64 %ext_short, i64* @var64, align 8
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; CHECK: ldrh w[[EXT:[0-9]+]], [sp, #16]
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; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
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%ext_int = zext i32 %int to i64
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store volatile i64 %ext_int, i64* @var64, align 8
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; CHECK: ldr w[[EXT:[0-9]+]], [sp, #24]
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; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
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store volatile i64 %long, i64* @var64, align 8
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; CHECK: str [[LONG]], [{{x[0-9]+}}, :lo12:var64]
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ret void
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}
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; Make sure the callee does extensions (in the absence of zext/sext
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; keyword on args) while we're here.
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define void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) {
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%ext_bool = zext i1 %bool to i64
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store volatile i64 %ext_bool, i64* @var64
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; CHECK: and [[EXT:x[0-9]+]], x0, #0x1
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; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
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%ext_char = sext i8 %char to i64
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store volatile i64 %ext_char, i64* @var64
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; CHECK: sxtb [[EXT:x[0-9]+]], w1
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; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
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%ext_short = zext i16 %short to i64
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store volatile i64 %ext_short, i64* @var64
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; CHECK: and [[EXT:x[0-9]+]], x2, #0xffff
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; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
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%ext_int = zext i32 %int to i64
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store volatile i64 %ext_int, i64* @var64
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; CHECK: uxtw [[EXT:x[0-9]+]], w3
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; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
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ret void
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}
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declare void @variadic(i32 %a, ...)
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; Under AAPCS variadic functions have the same calling convention as
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; others. The extra arguments should go in registers rather than on the stack.
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define void @test_variadic() {
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call void(i32, ...)* @variadic(i32 0, i64 1, double 2.0)
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; CHECK: fmov d0, #2.0
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; CHECK: orr w1, wzr, #0x1
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; CHECK: bl variadic
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ret void
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}
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; We weren't marking x7 as used after deciding that the i128 didn't fit into
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; registers and putting the first half on the stack, so the *second* half went
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; into x7. Yuck!
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define i128 @test_i128_shadow([7 x i64] %x0_x6, i128 %sp) {
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; CHECK-LABEL: test_i128_shadow:
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; CHECK: ldp x0, x1, [sp]
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ret i128 %sp
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}
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