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2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
52 lines
1.5 KiB
LLVM
52 lines
1.5 KiB
LLVM
; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
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; Extract of an upper half of a vector is an "ext.16b v0, v0, v0, #8" insn.
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define <8 x i8> @v8i8(<16 x i8> %a) nounwind {
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; CHECK: v8i8
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; CHECK: ext.16b v0, v0, v0, #8
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; CHECK: ret
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%ret = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <8 x i8> %ret
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}
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define <4 x i16> @v4i16(<8 x i16> %a) nounwind {
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; CHECK-LABEL: v4i16:
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; CHECK: ext.16b v0, v0, v0, #8
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; CHECK: ret
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%ret = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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ret <4 x i16> %ret
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}
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define <2 x i32> @v2i32(<4 x i32> %a) nounwind {
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; CHECK-LABEL: v2i32:
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; CHECK: ext.16b v0, v0, v0, #8
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; CHECK: ret
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%ret = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3>
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ret <2 x i32> %ret
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}
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define <1 x i64> @v1i64(<2 x i64> %a) nounwind {
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; CHECK-LABEL: v1i64:
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; CHECK: ext.16b v0, v0, v0, #8
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; CHECK: ret
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%ret = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> <i32 1>
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ret <1 x i64> %ret
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}
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define <2 x float> @v2f32(<4 x float> %a) nounwind {
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; CHECK-LABEL: v2f32:
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; CHECK: ext.16b v0, v0, v0, #8
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; CHECK: ret
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%ret = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> <i32 2, i32 3>
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ret <2 x float> %ret
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}
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define <1 x double> @v1f64(<2 x double> %a) nounwind {
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; CHECK-LABEL: v1f64:
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; CHECK: ext.16b v0, v0, v0, #8
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; CHECK: ret
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%ret = shufflevector <2 x double> %a, <2 x double> %a, <1 x i32> <i32 1>
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ret <1 x double> %ret
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}
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