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2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
18 lines
409 B
LLVM
18 lines
409 B
LLVM
; RUN: llc < %s -march=arm64 | FileCheck %s
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; Optimize (x > -1) to (x >= 0) etc.
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; Optimize (cmp (add / sub), 0): eliminate the subs used to update flag
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; for comparison only
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; rdar://10233472
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define i32 @t1(i64 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: t1:
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; CHECK-NOT: movn
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; CHECK: cmp x0, #0
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; CHECK: csinc w0, wzr, wzr, lt
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%cmp = icmp sgt i64 %a, -1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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