Nadav Rotem 18cdee3bee On AVX, we can load v8i32 at a time. The bug happens when two uneven loads are used. ... When we load the v12i32 type, the GenWidenVectorLoads method generates two loads: v8i32 and v4i32 and attempts to use CONCAT_VECTORS to join them. In this fix I concat undef values to widen the smaller value. The test "widen_load-2.ll" also exposes this bug on AVX. llvm-svn: 147964		2012-01-11 20:19:17 +00:00
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ARM	ARM Ld/St Optimizer fix.	2012-01-11 03:56:08 +00:00
CBackend	Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic.	2011-11-27 06:54:59 +00:00
CellSPU
CPP
Generic	Manually upgrade the test suite to specify the flag to cttz and ctlz.	2011-12-12 11:59:10 +00:00
Hexagon	Hexagon: Fix a nasty order-of-initialization bug.	2011-12-16 19:08:59 +00:00
MBlaze
Mips	Have getRegForInlineAsmConstraint return the correct register class when target	2012-01-04 02:45:01 +00:00
MSP430	Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic.	2011-11-27 06:54:59 +00:00
PowerPC	Cleanup stack/frame register define/kill states. This fixes two bugs:	2011-12-30 00:34:00 +00:00
PTX	PTX: Continue to fix up the register mess.	2011-12-06 17:39:48 +00:00
SPARC	Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since	2011-12-03 21:24:48 +00:00
Thumb	Fix more places which should be checking for iOS, not darwin.	2012-01-04 01:55:04 +00:00
Thumb2	Consider unknown alignment caused by OptimizeThumb2Instructions().	2012-01-10 22:32:14 +00:00
X86	On AVX, we can load v8i32 at a time. The bug happens when two uneven loads are used.	2012-01-11 20:19:17 +00:00
XCore	FileCheck hygiene.	2012-01-05 00:43:34 +00:00