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https://github.com/RPCS3/llvm-mirror.git
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58b7cca257
llvm-svn: 100214
421 lines
15 KiB
C++
421 lines
15 KiB
C++
//===- MBlazeRegisterInfo.cpp - MBlaze Register Information -== -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MBlaze implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mblaze-reg-info"
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#include "MBlaze.h"
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#include "MBlazeSubtarget.h"
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#include "MBlazeRegisterInfo.h"
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#include "MBlazeMachineFunction.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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MBlazeRegisterInfo::
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MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
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: MBlazeGenRegisterInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
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Subtarget(ST), TII(tii) {}
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// MBlaze::R0, return the number that it corresponds to (e.g. 0).
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unsigned MBlazeRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
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switch (RegEnum) {
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case MBlaze::R0 : case MBlaze::F0 : return 0;
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case MBlaze::R1 : case MBlaze::F1 : return 1;
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case MBlaze::R2 : case MBlaze::F2 : return 2;
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case MBlaze::R3 : case MBlaze::F3 : return 3;
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case MBlaze::R4 : case MBlaze::F4 : return 4;
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case MBlaze::R5 : case MBlaze::F5 : return 5;
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case MBlaze::R6 : case MBlaze::F6 : return 6;
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case MBlaze::R7 : case MBlaze::F7 : return 7;
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case MBlaze::R8 : case MBlaze::F8 : return 8;
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case MBlaze::R9 : case MBlaze::F9 : return 9;
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case MBlaze::R10 : case MBlaze::F10 : return 10;
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case MBlaze::R11 : case MBlaze::F11 : return 11;
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case MBlaze::R12 : case MBlaze::F12 : return 12;
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case MBlaze::R13 : case MBlaze::F13 : return 13;
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case MBlaze::R14 : case MBlaze::F14 : return 14;
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case MBlaze::R15 : case MBlaze::F15 : return 15;
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case MBlaze::R16 : case MBlaze::F16 : return 16;
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case MBlaze::R17 : case MBlaze::F17 : return 17;
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case MBlaze::R18 : case MBlaze::F18 : return 18;
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case MBlaze::R19 : case MBlaze::F19 : return 19;
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case MBlaze::R20 : case MBlaze::F20 : return 20;
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case MBlaze::R21 : case MBlaze::F21 : return 21;
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case MBlaze::R22 : case MBlaze::F22 : return 22;
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case MBlaze::R23 : case MBlaze::F23 : return 23;
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case MBlaze::R24 : case MBlaze::F24 : return 24;
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case MBlaze::R25 : case MBlaze::F25 : return 25;
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case MBlaze::R26 : case MBlaze::F26 : return 26;
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case MBlaze::R27 : case MBlaze::F27 : return 27;
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case MBlaze::R28 : case MBlaze::F28 : return 28;
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case MBlaze::R29 : case MBlaze::F29 : return 29;
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case MBlaze::R30 : case MBlaze::F30 : return 30;
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case MBlaze::R31 : case MBlaze::F31 : return 31;
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default: llvm_unreachable("Unknown register number!");
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}
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return 0; // Not reached
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}
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/// getRegisterFromNumbering - Given the enum value for some register, e.g.
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/// MBlaze::R0, return the number that it corresponds to (e.g. 0).
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unsigned MBlazeRegisterInfo::getRegisterFromNumbering(unsigned Reg) {
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switch (Reg) {
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case 0 : return MBlaze::R0;
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case 1 : return MBlaze::R1;
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case 2 : return MBlaze::R2;
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case 3 : return MBlaze::R3;
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case 4 : return MBlaze::R4;
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case 5 : return MBlaze::R5;
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case 6 : return MBlaze::R6;
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case 7 : return MBlaze::R7;
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case 8 : return MBlaze::R8;
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case 9 : return MBlaze::R9;
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case 10 : return MBlaze::R10;
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case 11 : return MBlaze::R11;
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case 12 : return MBlaze::R12;
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case 13 : return MBlaze::R13;
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case 14 : return MBlaze::R14;
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case 15 : return MBlaze::R15;
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case 16 : return MBlaze::R16;
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case 17 : return MBlaze::R17;
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case 18 : return MBlaze::R18;
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case 19 : return MBlaze::R19;
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case 20 : return MBlaze::R20;
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case 21 : return MBlaze::R21;
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case 22 : return MBlaze::R22;
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case 23 : return MBlaze::R23;
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case 24 : return MBlaze::R24;
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case 25 : return MBlaze::R25;
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case 26 : return MBlaze::R26;
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case 27 : return MBlaze::R27;
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case 28 : return MBlaze::R28;
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case 29 : return MBlaze::R29;
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case 30 : return MBlaze::R30;
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case 31 : return MBlaze::R31;
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default: llvm_unreachable("Unknown register number!");
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}
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return 0; // Not reached
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}
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unsigned MBlazeRegisterInfo::getPICCallReg() {
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return MBlaze::R20;
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}
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//===----------------------------------------------------------------------===//
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// Callee Saved Registers methods
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//===----------------------------------------------------------------------===//
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/// MBlaze Callee Saved Registers
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const unsigned* MBlazeRegisterInfo::
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getCalleeSavedRegs(const MachineFunction *MF) const {
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// MBlaze callee-save register range is R20 - R31
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static const unsigned CalleeSavedRegs[] = {
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MBlaze::R20, MBlaze::R21, MBlaze::R22, MBlaze::R23,
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MBlaze::R24, MBlaze::R25, MBlaze::R26, MBlaze::R27,
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MBlaze::R28, MBlaze::R29, MBlaze::R30, MBlaze::R31,
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0
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};
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return CalleeSavedRegs;
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}
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/// MBlaze Callee Saved Register Classes
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const TargetRegisterClass* const* MBlazeRegisterInfo::
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getCalleeSavedRegClasses(const MachineFunction *MF) const {
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static const TargetRegisterClass * const CalleeSavedRC[] = {
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&MBlaze::CPURegsRegClass, &MBlaze::CPURegsRegClass,
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&MBlaze::CPURegsRegClass, &MBlaze::CPURegsRegClass,
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&MBlaze::CPURegsRegClass, &MBlaze::CPURegsRegClass,
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&MBlaze::CPURegsRegClass, &MBlaze::CPURegsRegClass,
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&MBlaze::CPURegsRegClass, &MBlaze::CPURegsRegClass,
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&MBlaze::CPURegsRegClass, &MBlaze::CPURegsRegClass,
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0
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};
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return CalleeSavedRC;
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}
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BitVector MBlazeRegisterInfo::
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getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(MBlaze::R0);
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Reserved.set(MBlaze::R1);
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Reserved.set(MBlaze::R2);
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Reserved.set(MBlaze::R13);
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Reserved.set(MBlaze::R14);
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Reserved.set(MBlaze::R15);
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Reserved.set(MBlaze::R16);
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Reserved.set(MBlaze::R17);
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Reserved.set(MBlaze::R18);
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Reserved.set(MBlaze::R19);
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return Reserved;
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}
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//===----------------------------------------------------------------------===//
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//
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// Stack Frame Processing methods
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// +----------------------------+
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//
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// The stack is allocated decrementing the stack pointer on
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// the first instruction of a function prologue. Once decremented,
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// all stack references are are done through a positive offset
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// from the stack/frame pointer, so the stack is considered
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// to grow up.
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//
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//===----------------------------------------------------------------------===//
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void MBlazeRegisterInfo::adjustMBlazeStackFrame(MachineFunction &MF) const {
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>();
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// See the description at MicroBlazeMachineFunction.h
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int TopCPUSavedRegOff = -1;
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// Adjust CPU Callee Saved Registers Area. Registers RA and FP must
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// be saved in this CPU Area there is the need. This whole Area must
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// be aligned to the default Stack Alignment requirements.
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unsigned StackOffset = MFI->getStackSize();
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unsigned RegSize = 4;
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// Replace the dummy '0' SPOffset by the negative offsets, as explained on
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// LowerFORMAL_ARGUMENTS. Leaving '0' for while is necessary to avoid
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// the approach done by calculateFrameObjectOffsets to the stack frame.
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MBlazeFI->adjustLoadArgsFI(MFI);
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MBlazeFI->adjustStoreVarArgsFI(MFI);
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if (hasFP(MF)) {
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MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
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StackOffset);
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MBlazeFI->setFPStackOffset(StackOffset);
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TopCPUSavedRegOff = StackOffset;
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StackOffset += RegSize;
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}
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if (MFI->hasCalls()) {
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MBlazeFI->setRAStackOffset(0);
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MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
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StackOffset);
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TopCPUSavedRegOff = StackOffset;
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StackOffset += RegSize;
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}
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// Update frame info
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MFI->setStackSize(StackOffset);
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// Recalculate the final tops offset. The final values must be '0'
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// if there isn't a callee saved register for CPU or FPU, otherwise
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// a negative offset is needed.
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if (TopCPUSavedRegOff >= 0)
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MBlazeFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset);
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}
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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bool MBlazeRegisterInfo::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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return NoFramePointerElim || MFI->hasVarSizedObjects();
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}
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// This function eliminate ADJCALLSTACKDOWN,
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// ADJCALLSTACKUP pseudo instructions
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void MBlazeRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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// Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
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MBB.erase(I);
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}
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// FrameIndex represent objects inside a abstract stack.
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// We must replace FrameIndex with an stack/frame pointer
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// direct reference.
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unsigned MBlazeRegisterInfo::
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eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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FrameIndexValue *Value, RegScavenger *RS) const {
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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unsigned i = 0;
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() &&
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"Instr doesn't have FrameIndex operand!");
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}
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unsigned oi = i == 2 ? 1 : 2;
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DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
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errs() << "<--------->\n" << MI);
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int FrameIndex = MI.getOperand(i).getIndex();
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int stackSize = MF.getFrameInfo()->getStackSize();
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int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
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<< "spOffset : " << spOffset << "\n"
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<< "stackSize : " << stackSize << "\n");
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// as explained on LowerFormalArguments, detect negative offsets
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// and adjust SPOffsets considering the final stack size.
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int Offset = (spOffset < 0) ? (stackSize - spOffset) : (spOffset + 4);
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Offset += MI.getOperand(oi).getImm();
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DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
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MI.getOperand(oi).ChangeToImmediate(Offset);
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MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
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return 0;
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}
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void MBlazeRegisterInfo::
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emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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// Get the right frame order for MBlaze.
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adjustMBlazeStackFrame(MF);
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// Get the number of bytes to allocate from the FrameInfo.
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unsigned StackSize = MFI->getStackSize();
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// No need to allocate space on the stack.
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if (StackSize == 0 && !MFI->hasCalls()) return;
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if (StackSize < 28 && MFI->hasCalls()) StackSize = 28;
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int FPOffset = MBlazeFI->getFPStackOffset();
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int RAOffset = MBlazeFI->getRAStackOffset();
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// Adjust stack : addi R1, R1, -imm
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BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADDI), MBlaze::R1)
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.addReg(MBlaze::R1).addImm(-StackSize);
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// Save the return address only if the function isnt a leaf one.
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// swi R15, R1, stack_loc
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if (MFI->hasCalls()) {
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BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI))
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.addReg(MBlaze::R15).addImm(RAOffset).addReg(MBlaze::R1);
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}
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// if framepointer enabled, save it and set it
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// to point to the stack pointer
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if (hasFP(MF)) {
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// swi R19, R1, stack_loc
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BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI))
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.addReg(MBlaze::R19).addImm(FPOffset).addReg(MBlaze::R1);
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// add R19, R1, R0
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BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADD), MBlaze::R19)
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.addReg(MBlaze::R1).addReg(MBlaze::R0);
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}
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}
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void MBlazeRegisterInfo::
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emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>();
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DebugLoc dl = MBBI->getDebugLoc();
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// Get the FI's where RA and FP are saved.
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int FPOffset = MBlazeFI->getFPStackOffset();
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int RAOffset = MBlazeFI->getRAStackOffset();
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// if framepointer enabled, restore it and restore the
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// stack pointer
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if (hasFP(MF)) {
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// add R1, R19, R0
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BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADD), MBlaze::R1)
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.addReg(MBlaze::R19).addReg(MBlaze::R0);
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// lwi R19, R1, stack_loc
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BuildMI(MBB, MBBI, dl, TII.get(MBlaze::LWI), MBlaze::R19)
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.addImm(FPOffset).addReg(MBlaze::R1);
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}
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// Restore the return address only if the function isnt a leaf one.
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// lwi R15, R1, stack_loc
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if (MFI->hasCalls()) {
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BuildMI(MBB, MBBI, dl, TII.get(MBlaze::LWI), MBlaze::R15)
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.addImm(RAOffset).addReg(MBlaze::R1);
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}
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// Get the number of bytes from FrameInfo
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int StackSize = (int) MFI->getStackSize();
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if (StackSize < 28 && MFI->hasCalls()) StackSize = 28;
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// adjust stack.
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// addi R1, R1, imm
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if (StackSize) {
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BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADDI), MBlaze::R1)
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.addReg(MBlaze::R1).addImm(StackSize);
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}
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}
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void MBlazeRegisterInfo::
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processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
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// Set the stack offset where GP must be saved/loaded from.
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>();
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if (MBlazeFI->needGPSaveRestore())
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MFI->setObjectOffset(MBlazeFI->getGPFI(), MBlazeFI->getGPStackOffset());
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}
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unsigned MBlazeRegisterInfo::getRARegister() const {
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return MBlaze::R15;
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}
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unsigned MBlazeRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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return hasFP(MF) ? MBlaze::R19 : MBlaze::R1;
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}
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unsigned MBlazeRegisterInfo::getEHExceptionRegister() const {
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llvm_unreachable("What is the exception register");
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return 0;
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}
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unsigned MBlazeRegisterInfo::getEHHandlerRegister() const {
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llvm_unreachable("What is the exception handler register");
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return 0;
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}
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int MBlazeRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
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llvm_unreachable("What is the dwarf register number");
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return -1;
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}
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#include "MBlazeGenRegisterInfo.inc"
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