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llvm-mirror/test/CodeGen/AArch64/GlobalISel
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Amara Emerson 9cc2f0a8e7 [AArch64][GlobalISel] Fix assert fail with unknown intrinsic. 
A call may have an intrinsic name but not have a valid intrinsic ID,
for example with llvm.invariant.group.barrier. If so, treat it as a
normal call like FastISel does.

llvm-svn: 321662
2018-01-02 18:56:39 +00:00
..
arm64-callingconv-ios.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
arm64-callingconv.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
arm64-fallback.ll [AArch64][GlobalISel] Enable GlobalISel at -O0 by default 2018-01-02 16:30:47 +00:00
arm64-irtranslator-stackprotect.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
arm64-irtranslator.ll Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64. 2017-12-05 05:52:07 +00:00
arm64-regbankselect.mir [AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR 2017-11-18 04:28:59 +00:00
call-translator-ios.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
call-translator.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
combine-anyext-crash.mir
debug-insts.ll [CodeGen] Always use printReg to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
dynamic-alloca.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
fp128-legalize-crash-pr35690.mir [GlobalISel][Legalizer] Fix crash when trying to lower G_FNEG of fp128 types. 2017-12-19 17:21:35 +00:00
gisel-abort.ll
gisel-commandline-option.ll [AArch64][GlobalISel] Enable GlobalISel at -O0 by default 2018-01-02 16:30:47 +00:00
gisel-fail-intermediate-legalizer.ll
inline-asm.ll
irtranslator-bitcast.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
irtranslator-exceptions.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
legalize-add.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-and.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-atomicrmw.mir [aarch64][globalisel] Add missing tests from r319216 2017-11-28 20:27:59 +00:00
legalize-cmp.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-cmpxchg-with-success.mir [aarch64][globalisel] Legalize G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMICRMW_* 2017-11-30 20:11:42 +00:00
legalize-cmpxchg.mir [aarch64][globalisel] Add missing tests from r319216 2017-11-28 20:27:59 +00:00
legalize-combines.mir GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 2017-12-01 08:19:10 +00:00
legalize-constant.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-div.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-exceptions.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
legalize-ext.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-extracts.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-fcmp.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-fneg.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-fptoi.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-gep.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-ignore-non-generic.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-inserts.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-itofp.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-load-store.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-merge-values.mir GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 2017-12-01 08:19:10 +00:00
legalize-mul.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-nonpowerof2eltsvec.mir GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 2017-12-01 08:19:10 +00:00
legalize-or.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-phi.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-pow.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-property.mir
legalize-rem.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-shift.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-simple.mir [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
legalize-sub.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-undef.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-unmerge-values.mir GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 2017-12-01 08:19:10 +00:00
legalize-vaarg.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-xor.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
lit.local.cfg
localizer-in-O0-pipeline.mir [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
localizer.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
no-regclass.mir GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 2017-12-01 08:19:10 +00:00
reg-bank-128bit.mir [GISel][AArch64]: Fix illegal Generic copies in tests 2017-10-23 22:53:04 +00:00
regbankselect-dbg-value.mir [CodeGen] Always use printReg to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
regbankselect-default.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
regbankselect-reg_sequence.mir
select-atomicrmw.mir [globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG, G_ATOMICRMW_* rules from SelectionDAG. 2017-11-28 22:07:05 +00:00
select-binop.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-bitcast-bigendian.mir [globalisel][tablegen] Add support for multi-insn emission 2017-11-01 19:57:57 +00:00
select-bitcast.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-br.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-bswap.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-cbz.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-cmpxchg.mir [globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG, G_ATOMICRMW_* rules from SelectionDAG. 2017-11-28 22:07:05 +00:00
select-constant.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-dbg-value.mir [CodeGen] Always use printReg to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
select-fma.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-fp-casts.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-imm.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-implicit-def.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-insert-extract.mir [MIRPrinter] Use %subreg.xxx syntax for subregister index operands 2017-11-06 21:46:06 +00:00
select-int-ext.mir [MIRPrinter] Use %subreg.xxx syntax for subregister index operands 2017-11-06 21:46:06 +00:00
select-int-ptr-casts.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-intrinsic-aarch64-hint.mir
select-intrinsic-aarch64-sdiv.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-intrinsic-crypto-aesmc.mir [globalisel][tablegen] Add support for multi-insn emission 2017-11-01 19:57:57 +00:00
select-load.mir [globalisel][tablegen] Add support for extload. 2017-11-13 18:30:23 +00:00
select-muladd.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-neon-vcvtfxu2fp.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-phi.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-pr32733.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-property.mir
select-store.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-trunc.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-xor.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
translate-gep.ll update_mir_test_checks: Accept IR as input as well as MIR 2017-12-19 00:49:04 +00:00
unknown-intrinsic.ll [AArch64][GlobalISel] Fix assert fail with unknown intrinsic. 2018-01-02 18:56:39 +00:00
varargs-ios-translator.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
vastart.ll MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
verify-regbankselected.mir [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
verify-selected.mir [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00