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d5cead992a
This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
54 lines
1.2 KiB
YAML
54 lines
1.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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define void @bswap_s32() { ret void }
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define void @bswap_s64() { ret void }
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...
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---
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name: bswap_s32
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %w0
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; CHECK-LABEL: name: bswap_s32
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
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; CHECK: [[REVWr:%[0-9]+]]:gpr32 = REVWr [[COPY]]
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; CHECK: %w0 = COPY [[REVWr]]
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%0(s32) = COPY %w0
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%1(s32) = G_BSWAP %0
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%w0 = COPY %1
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...
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---
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name: bswap_s64
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: bswap_s64
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
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; CHECK: [[REVXr:%[0-9]+]]:gpr64 = REVXr [[COPY]]
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; CHECK: %x0 = COPY [[REVXr]]
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%0(s64) = COPY %x0
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%1(s64) = G_BSWAP %0
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%x0 = COPY %1
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...
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