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30 lines
1.1 KiB
LLVM
30 lines
1.1 KiB
LLVM
; RUN: llc < %s -x86-experimental-vector-shuffle-lowering=false -mattr=+avx2 | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-darwin"
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; PR21876
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; The old shuffle lowering sometimes generates VZEXT nodes with both input
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; and output same-sized types, here 256-bits. For instance, a v8i8 to v8i32
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; zero-extend would become a (v8i32 (VZEXT v32i8)) node, which can't happen
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; otherwise. The companion commit r223996 added those patterns temporarily.
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; This test, along with the VR256 for AVX2 PMOVXrr instructions, should be
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; removed once the old vector shuffle lowering goes away.
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define void @test_avx2_pmovx_256(<8 x i8>* %tmp64, <8 x float>* %tmp75) {
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; CHECK-LABEL: test_avx2_pmovx_256
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; We really don't care about the generated code.
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; CHECK: vpmovzxbd
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; CHECK: vpbroadcastd
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; CHECK: vpand
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; CHECK: vcvtdq2ps
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; CHECK: vmovups
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; CHECK: vzeroupper
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; CHECK: retq
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%wide.load458 = load <8 x i8>* %tmp64, align 1
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%tmp68 = uitofp <8 x i8> %wide.load458 to <8 x float>
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store <8 x float> %tmp68, <8 x float>* %tmp75, align 4
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ret void
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}
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