1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
llvm-mirror/test/CodeGen/CellSPU/call.ll
Kalle Raiskila 2001fd19b9 Mark the SPU 'lr' instruction to never have side effects.
This allows the fast regiser allocator to remove redundant 
register moves.
Update a set of tests that depend on the register allocator
to be linear scan. 

llvm-svn: 106420
2010-06-21 15:08:16 +00:00

32 lines
790 B
LLVM

; RUN: llc < %s -march=cellspu -regalloc=linearscan > %t1.s
; RUN: grep brsl %t1.s | count 1
; RUN: grep brasl %t1.s | count 1
; RUN: grep stqd %t1.s | count 80
; RUN: llc < %s -march=cellspu | FileCheck %s
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"
define i32 @main() {
entry:
%a = call i32 @stub_1(i32 1, float 0x400921FA00000000)
call void @extern_stub_1(i32 %a, i32 4)
ret i32 %a
}
declare void @extern_stub_1(i32, i32)
define i32 @stub_1(i32 %x, float %y) {
; CHECK: il $3, 0
; CHECK: bi $lr
entry:
ret i32 0
}
; vararg call: ensure that all caller-saved registers are spilled to the
; stack:
define i32 @stub_2(...) {
entry:
ret i32 0
}