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182b0cd903
This is a follow-up for: D98604 [MCA] Ensure that writes occur in-order When instructions are aligned by the order of writes, they retire in-order naturally. There is no need for an RCU, so it is disabled. Differential Revision: https://reviews.llvm.org/D98628
90 lines
3.4 KiB
C++
90 lines
3.4 KiB
C++
//===---------------------------- Context.cpp -------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file defines a class for holding ownership of various simulated
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/// hardware units. A Context also provides a utility routine for constructing
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/// a default out-of-order pipeline with fetch, dispatch, execute, and retire
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/// stages.
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///
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//===----------------------------------------------------------------------===//
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#include "llvm/MCA/Context.h"
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#include "llvm/MCA/HardwareUnits/RegisterFile.h"
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#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
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#include "llvm/MCA/HardwareUnits/Scheduler.h"
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#include "llvm/MCA/Stages/DispatchStage.h"
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#include "llvm/MCA/Stages/EntryStage.h"
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#include "llvm/MCA/Stages/ExecuteStage.h"
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#include "llvm/MCA/Stages/InOrderIssueStage.h"
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#include "llvm/MCA/Stages/MicroOpQueueStage.h"
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#include "llvm/MCA/Stages/RetireStage.h"
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namespace llvm {
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namespace mca {
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std::unique_ptr<Pipeline>
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Context::createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr) {
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const MCSchedModel &SM = STI.getSchedModel();
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if (!SM.isOutOfOrder())
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return createInOrderPipeline(Opts, SrcMgr);
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// Create the hardware units defining the backend.
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auto RCU = std::make_unique<RetireControlUnit>(SM);
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auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
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auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
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Opts.StoreQueueSize, Opts.AssumeNoAlias);
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auto HWS = std::make_unique<Scheduler>(SM, *LSU);
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// Create the pipeline stages.
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auto Fetch = std::make_unique<EntryStage>(SrcMgr);
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auto Dispatch = std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth,
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*RCU, *PRF);
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auto Execute =
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std::make_unique<ExecuteStage>(*HWS, Opts.EnableBottleneckAnalysis);
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auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU);
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// Pass the ownership of all the hardware units to this Context.
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addHardwareUnit(std::move(RCU));
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addHardwareUnit(std::move(PRF));
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addHardwareUnit(std::move(LSU));
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addHardwareUnit(std::move(HWS));
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// Build the pipeline.
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auto StagePipeline = std::make_unique<Pipeline>();
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StagePipeline->appendStage(std::move(Fetch));
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if (Opts.MicroOpQueueSize)
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StagePipeline->appendStage(std::make_unique<MicroOpQueueStage>(
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Opts.MicroOpQueueSize, Opts.DecodersThroughput));
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StagePipeline->appendStage(std::move(Dispatch));
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StagePipeline->appendStage(std::move(Execute));
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StagePipeline->appendStage(std::move(Retire));
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return StagePipeline;
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}
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std::unique_ptr<Pipeline>
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Context::createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr) {
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const MCSchedModel &SM = STI.getSchedModel();
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auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
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auto Entry = std::make_unique<EntryStage>(SrcMgr);
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auto InOrderIssue = std::make_unique<InOrderIssueStage>(*PRF, SM, STI);
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auto StagePipeline = std::make_unique<Pipeline>();
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StagePipeline->appendStage(std::move(Entry));
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StagePipeline->appendStage(std::move(InOrderIssue));
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addHardwareUnit(std::move(PRF));
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return StagePipeline;
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}
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} // namespace mca
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} // namespace llvm
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