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98be3942ed
This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. llvm-svn: 216225
64 lines
1.3 KiB
LLVM
64 lines
1.3 KiB
LLVM
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
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;; Test returns.
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define void @t0() nounwind ssp {
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entry:
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; CHECK: t0
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; CHECK: ret
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ret void
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}
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define i32 @t1(i32 %a) nounwind ssp {
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entry:
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; CHECK: t1
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; CHECK: str w0, [sp, #12]
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; CHECK-NEXT: ldr w0, [sp, #12]
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; CHECK: ret
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%a.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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%tmp = load i32* %a.addr, align 4
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ret i32 %tmp
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}
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define i64 @t2(i64 %a) nounwind ssp {
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entry:
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; CHECK: t2
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; CHECK: str x0, [sp, #8]
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; CHECK-NEXT: ldr x0, [sp, #8]
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; CHECK: ret
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%a.addr = alloca i64, align 8
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store i64 %a, i64* %a.addr, align 8
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%tmp = load i64* %a.addr, align 8
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ret i64 %tmp
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}
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define signext i16 @ret_i16(i16 signext %a) nounwind {
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entry:
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; CHECK: @ret_i16
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; CHECK: sxth w0, w0
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%a.addr = alloca i16, align 1
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store i16 %a, i16* %a.addr, align 1
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%0 = load i16* %a.addr, align 1
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ret i16 %0
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}
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define signext i8 @ret_i8(i8 signext %a) nounwind {
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entry:
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; CHECK: @ret_i8
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; CHECK: sxtb w0, w0
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%a.addr = alloca i8, align 1
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store i8 %a, i8* %a.addr, align 1
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%0 = load i8* %a.addr, align 1
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ret i8 %0
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}
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define signext i1 @ret_i1(i1 signext %a) nounwind {
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entry:
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; CHECK: @ret_i1
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; CHECK: and w0, w0, #0x1
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%a.addr = alloca i1, align 1
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store i1 %a, i1* %a.addr, align 1
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%0 = load i1* %a.addr, align 1
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ret i1 %0
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}
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