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ca0f4dc4f0
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
93 lines
2.8 KiB
LLVM
93 lines
2.8 KiB
LLVM
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
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define i32 @vmax_u8x8(<8 x i8> %a) nounwind ssp {
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; CHECK-LABEL: vmax_u8x8:
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; CHECK: umaxv.8b b[[REG:[0-9]+]], v0
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; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
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; CHECK-NOT: and
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; CHECK: cbz [[REG2]],
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entry:
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a) nounwind
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%tmp = trunc i32 %vmaxv.i to i8
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%tobool = icmp eq i8 %tmp, 0
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br i1 %tobool, label %return, label %if.then
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if.then:
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
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br label %return
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return:
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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declare i32 @bar(...)
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define i32 @vmax_u4x16(<4 x i16> %a) nounwind ssp {
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; CHECK-LABEL: vmax_u4x16:
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; CHECK: umaxv.4h h[[REG:[0-9]+]], v0
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; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
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; CHECK-NOT: and
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; CHECK: cbz [[REG2]],
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entry:
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a) nounwind
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%tmp = trunc i32 %vmaxv.i to i16
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%tobool = icmp eq i16 %tmp, 0
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br i1 %tobool, label %return, label %if.then
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if.then:
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
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br label %return
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return:
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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define i32 @vmax_u8x16(<8 x i16> %a) nounwind ssp {
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; CHECK-LABEL: vmax_u8x16:
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; CHECK: umaxv.8h h[[REG:[0-9]+]], v0
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; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
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; CHECK-NOT: and
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; CHECK: cbz [[REG2]],
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entry:
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a) nounwind
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%tmp = trunc i32 %vmaxv.i to i16
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%tobool = icmp eq i16 %tmp, 0
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br i1 %tobool, label %return, label %if.then
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if.then:
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
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br label %return
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return:
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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define i32 @vmax_u16x8(<16 x i8> %a) nounwind ssp {
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; CHECK-LABEL: vmax_u16x8:
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; CHECK: umaxv.16b b[[REG:[0-9]+]], v0
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; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
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; CHECK-NOT: and
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; CHECK: cbz [[REG2]],
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entry:
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a) nounwind
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%tmp = trunc i32 %vmaxv.i to i8
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%tobool = icmp eq i8 %tmp, 0
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br i1 %tobool, label %return, label %if.then
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if.then:
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
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br label %return
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return:
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) nounwind readnone
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declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>) nounwind readnone
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declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>) nounwind readnone
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declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) nounwind readnone
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