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b401fd4c9e
Also avoid locals evicting locals just because they want a cheaper register. Problem: MI Sched knows exactly how many registers we have and assumes they can be colored. In cases where we have large blocks, usually from unrolled loops, greedy coloring fails. This is a source of "regressions" from the MI Scheduler on x86. I noticed this issue on x86 where we have long chains of two-address defs in the same live range. It's easy to see this in matrix multiplication benchmarks like IRSmk and even the unit test misched-matmul.ll. A fundamental difference between the LLVM register allocator and conventional graph coloring is that in our model a live range can't discover its neighbors, it can only verify its neighbors. That's why we initially went for greedy coloring and added eviction to deal with the hard cases. However, for singly defined and two-address live ranges, we can optimally color without visiting neighbors simply by processing the live ranges in instruction order. Other beneficial side effects: It is much easier to understand and debug regalloc for large blocks when the live ranges are allocated in order. Yes, global allocation is still very confusing, but it's nice to be able to comprehend what happened locally. Heuristics could be added to bias register assignment based on instruction locality (think late register pairing, banks...). Intuituvely this will make some test cases that are on the threshold of register pressure more stable. llvm-svn: 187139
77 lines
2.8 KiB
LLVM
77 lines
2.8 KiB
LLVM
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=1
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=2
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=3
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=4
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@x = global float 0x41F487E980000000, align 4
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@dx = global double 0x41CDCC8BC4800000, align 8
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@cx = global { float, float } { float 1.000000e+00, float 9.900000e+01 }, align 4
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@dcx = global { double, double } { double 0x42CE5E14A412B480, double 0x423AA4C580DB0000 }, align 8
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define float @foox() {
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entry:
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%0 = load float* @x, align 4
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ret float %0
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; 1: .ent foox
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; 1: lw $2, %lo(x)(${{[0-9]+}})
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; 1: jal __mips16_ret_sf
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}
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define double @foodx() {
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entry:
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%0 = load double* @dx, align 8
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ret double %0
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; 1: .ent foodx
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; 1: lw $2, %lo(dx)(${{[0-9]+}})
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; 1: jal __mips16_ret_df
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; 2: .ent foodx
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; 2: lw $3, 4(${{[0-9]+}})
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; 2: jal __mips16_ret_df
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}
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define { float, float } @foocx() {
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entry:
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%retval = alloca { float, float }, align 4
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%cx.real = load float* getelementptr inbounds ({ float, float }* @cx, i32 0, i32 0)
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%cx.imag = load float* getelementptr inbounds ({ float, float }* @cx, i32 0, i32 1)
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%real = getelementptr inbounds { float, float }* %retval, i32 0, i32 0
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%imag = getelementptr inbounds { float, float }* %retval, i32 0, i32 1
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store float %cx.real, float* %real
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store float %cx.imag, float* %imag
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%0 = load { float, float }* %retval
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ret { float, float } %0
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; 1: .ent foocx
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; 1: lw $2, %lo(cx)(${{[0-9]+}})
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; 1: jal __mips16_ret_sc
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; 2: .ent foocx
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; 2: lw $3, 4(${{[0-9]+}})
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; 2: jal __mips16_ret_sc
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}
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define { double, double } @foodcx() {
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entry:
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%retval = alloca { double, double }, align 8
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%dcx.real = load double* getelementptr inbounds ({ double, double }* @dcx, i32 0, i32 0)
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%dcx.imag = load double* getelementptr inbounds ({ double, double }* @dcx, i32 0, i32 1)
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%real = getelementptr inbounds { double, double }* %retval, i32 0, i32 0
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%imag = getelementptr inbounds { double, double }* %retval, i32 0, i32 1
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store double %dcx.real, double* %real
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store double %dcx.imag, double* %imag
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%0 = load { double, double }* %retval
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ret { double, double } %0
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; 1: .ent foodcx
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; 1: lw ${{[0-9]}}, %lo(dcx)(${{[0-9]+}})
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; 1: jal __mips16_ret_dc
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; 2: .ent foodcx
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; 2: lw ${{[0-9]}}, 4(${{[0-9]+}})
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; 2: jal __mips16_ret_dc
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; 3: .ent foodcx
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; 3: lw $4, 8(${{[0-9]+}})
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; 3: jal __mips16_ret_dc
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; 4: .ent foodcx
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; 4: lw $5, 12(${{[0-9]+}})
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; 4: jal __mips16_ret_dc
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}
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