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030e941124
SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16 $T8 shows up as register $24 when emitted from C++ code so we had to change some tests that were already there for this functionality. llvm-svn: 175593
25 lines
708 B
LLVM
25 lines
708 B
LLVM
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@i = global i32 0, align 4
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@j = global i32 99, align 4
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@r1 = common global i32 0, align 4
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@r2 = common global i32 0, align 4
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define void @test() nounwind {
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entry:
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%0 = load i32* @i, align 4
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%cmp = icmp eq i32 %0, 0
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @r1, align 4
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; 16: sltiu ${{[0-9]+}}, 1
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; 16: move ${{[0-9]+}}, $24
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%1 = load i32* @j, align 4
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%cmp1 = icmp eq i32 %1, 99
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%conv2 = zext i1 %cmp1 to i32
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store i32 %conv2, i32* @r2, align 4
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; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
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; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
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; 16: move ${{[0-9]+}}, $24
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ret void
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}
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