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e7eb74ef39
Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. llvm-svn: 77897
41 lines
971 B
LLVM
41 lines
971 B
LLVM
; RUN: llvm-as < %s | llc -march=bfin > %t
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; XFAIL: *
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; Assertion failed: (isUsed(Reg) && "Using an undefined register!"),
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; function forward, file RegisterScavenging.cpp, line 259.
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; The DAG combiner may sometimes create illegal i16 SETCC operations when run
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; after LegalizeOps. Try to tease out all the optimizations in
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; TargetLowering::SimplifySetCC.
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@x = external global i16
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@y = external global i16
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declare i16 @llvm.ctlz.i16(i16)
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; Case (srl (ctlz x), 5) == const
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; Note: ctlz is promoted, so this test does not catch the DAG combiner
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define i1 @srl_ctlz_const() {
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%x = load i16* @x
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%c = call i16 @llvm.ctlz.i16(i16 %x)
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%s = lshr i16 %c, 4
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%r = icmp eq i16 %s, 1
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ret i1 %r
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}
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; Case (zext x) == const
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define i1 @zext_const() {
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%x = load i16* @x
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%r = icmp ugt i16 %x, 1
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ret i1 %r
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}
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; Case (sext x) == const
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define i1 @sext_const() {
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%x = load i16* @x
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%y = add i16 %x, 1
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%x2 = sext i16 %y to i32
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%r = icmp ne i32 %x2, -1
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ret i1 %r
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}
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