Sanjay Patel e7f59bf4cc [InstCombine] sink sext after ashr ... Narrow ops are better for bit-tracking, and in the case of vectors, may enable better codegen. As the trunc test shows, this can allow follow-on simplifications. There's a block of code in visitTrunc that deals with shifted ops with FIXME comments. It may be possible to remove some of that now, but I want to make sure there are no problems with this step first. http://rise4fun.com/Alive/Y3a Name: hoist_ashr_ahead_of_sext_1 %s = sext i8 %x to i32 %r = ashr i32 %s, 3 ; shift value is < than source bit width => %a = ashr i8 %x, 3 %r = sext i8 %a to i32 Name: hoist_ashr_ahead_of_sext_2 %s = sext i8 %x to i32 %r = ashr i32 %s, 8 ; shift value is >= than source bit width => %a = ashr i8 %x, 7 ; so clamp this shift value %r = sext i8 %a to i32 Name: junc_the_trunc %a = sext i16 %v to i32 %s = ashr i32 %a, 18 %t = trunc i32 %s to i16 => %t = ashr i16 %v, 15 llvm-svn: 310942		2017-08-15 18:25:52 +00:00
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Analysis	[Dominators] Include infinite loops in PostDominatorTree	2017-08-15 18:14:57 +00:00
Assembler
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Bitcode	Add strictfp attribute to prevent unwanted optimizations of libm calls	2017-08-14 21:15:13 +00:00
BugPoint
CodeGen	[Dominators] Include infinite loops in PostDominatorTree	2017-08-15 18:14:57 +00:00
DebugInfo	[llvm-dwarfdump] - Print section name and index when dumping .debug_info ranges	2017-08-15 12:32:54 +00:00
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MC	[RISCV] Add RISCVInstPrinter and basic MC assembler tests	2017-08-15 13:08:29 +00:00
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TableGen	Revert r310919 - [globalisel][tablegen] Support zero-instruction emission.	2017-08-15 15:10:31 +00:00
ThinLTO/X86
tools	[llvm-cov] Add an option which maps the location of source directories on another machine to your local copies	2017-08-14 10:20:12 +00:00
Transforms	[InstCombine] sink sext after ashr	2017-08-15 18:25:52 +00:00
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