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09e241eb0f
Summary: In this implementation, LiveIntervalAnalysis invents a few register masks on basic block boundaries that preserve no registers. The nice thing about this is that it prevents the prologue inserter from thinking it needs to spill all XMM CSRs, because it doesn't see any explicit physreg defs in the MI. Reviewers: MatzeB, qcolombet, JosephTremoulet, majnemer Subscribers: MatzeB, llvm-commits Differential Revision: http://reviews.llvm.org/D14407 llvm-svn: 252318
145 lines
5.2 KiB
C++
145 lines
5.2 KiB
C++
//===-- X86RegisterInfo.h - X86 Register Information Impl -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86REGISTERINFO_H
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#define LLVM_LIB_TARGET_X86_X86REGISTERINFO_H
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#include "llvm/Target/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "X86GenRegisterInfo.inc"
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namespace llvm {
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class Triple;
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class X86RegisterInfo final : public X86GenRegisterInfo {
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private:
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/// Is64Bit - Is the target 64-bits.
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///
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bool Is64Bit;
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/// IsWin64 - Is the target on of win64 flavours
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///
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bool IsWin64;
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/// SlotSize - Stack slot size in bytes.
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///
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unsigned SlotSize;
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/// StackPtr - X86 physical register used as stack ptr.
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///
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unsigned StackPtr;
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/// FramePtr - X86 physical register used as frame ptr.
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///
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unsigned FramePtr;
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/// BasePtr - X86 physical register used as a base ptr in complex stack
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/// frames. I.e., when we need a 3rd base, not just SP and FP, due to
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/// variable size stack objects.
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unsigned BasePtr;
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public:
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X86RegisterInfo(const Triple &TT);
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// FIXME: This should be tablegen'd like getDwarfRegNum is
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int getSEHRegNum(unsigned i) const;
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/// Code Generation virtual methods...
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///
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
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/// getMatchingSuperRegClass - Return a subclass of the specified register
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/// class A so that each register in it has a sub-register of the
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/// specified sub-register index which is in the specified register class B.
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const TargetRegisterClass *
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getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B,
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unsigned Idx) const override;
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const TargetRegisterClass *
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getSubClassWithSubReg(const TargetRegisterClass *RC,
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unsigned Idx) const override;
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const TargetRegisterClass *
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getLargestLegalSuperClass(const TargetRegisterClass *RC,
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const MachineFunction &MF) const override;
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/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
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/// values.
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const TargetRegisterClass *
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getPointerRegClass(const MachineFunction &MF,
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unsigned Kind = 0) const override;
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/// getCrossCopyRegClass - Returns a legal register class to copy a register
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/// in the specified class to or from. Returns NULL if it is possible to copy
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/// between a two registers of the specified class.
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const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const override;
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/// getCalleeSavedRegs - Return a null-terminated list of all of the
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/// callee-save registers on this target.
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const MCPhysReg *
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getCalleeSavedRegs(const MachineFunction* MF) const override;
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const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const override;
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const uint32_t *getNoPreservedMask() const override;
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/// getReservedRegs - Returns a bitset indexed by physical register number
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/// indicating if a register is a special register that has particular uses and
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/// should be considered unavailable at all times, e.g. SP, RA. This is used by
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/// register scavenger to determine what registers are free.
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
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bool hasBasePointer(const MachineFunction &MF) const;
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bool canRealignStack(const MachineFunction &MF) const override;
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bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
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int &FrameIdx) const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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// Debug information queries.
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const;
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unsigned getStackRegister() const { return StackPtr; }
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unsigned getBaseRegister() const { return BasePtr; }
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// FIXME: Move to FrameInfok
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unsigned getSlotSize() const { return SlotSize; }
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};
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/// Returns the sub or super register of a specific X86 register.
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/// e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) returns X86::AX.
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/// Aborts on error.
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unsigned getX86SubSuperRegister(unsigned, MVT::SimpleValueType, bool High=false);
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/// Returns the sub or super register of a specific X86 register.
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/// Like getX86SubSuperRegister() but returns 0 on error.
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unsigned getX86SubSuperRegisterOrZero(unsigned, MVT::SimpleValueType,
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bool High = false);
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//get512BitRegister - X86 utility - returns 512-bit super register
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unsigned get512BitSuperRegister(unsigned Reg);
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} // End llvm namespace
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#endif
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