mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-23 21:13:02 +02:00
319cba0069
Change the syntax to use `%0.sub8` to denote a subregister. This seems like a more natural fit to denote subregisters; I also plan to introduce a new ":classname" syntax in upcoming patches to denote the register class of a vreg. Note that this commit disallows plain identifiers to start with a '.' character. This shouldn't affect anything as external names/IR references are all prefixed with '$'/'%', plain identifiers are only used for instruction names, register mask names and subreg indexes. Differential Revision: https://reviews.llvm.org/D22390 llvm-svn: 276815
31 lines
978 B
YAML
31 lines
978 B
YAML
# RUN: llc -march=amdgcn -run-pass rename-independent-subregs -o - %s | FileCheck %s
|
|
--- |
|
|
define void @test0() { ret void }
|
|
...
|
|
---
|
|
# In the test below we have two independent def+use pairs of subregister1 which
|
|
# can be moved to a new virtual register. The third def of sub1 however is used
|
|
# in combination with sub0 and needs to stay with the original vreg.
|
|
# CHECK-LABEL: name: test0
|
|
# CHECK: S_NOP 0, implicit-def undef %0.sub0
|
|
# CHECK: S_NOP 0, implicit-def undef %2.sub1
|
|
# CHECK: S_NOP 0, implicit %2.sub1
|
|
# CHECK: S_NOP 0, implicit-def undef %1.sub1
|
|
# CHECK: S_NOP 0, implicit %1.sub1
|
|
# CHECK: S_NOP 0, implicit-def %0.sub1
|
|
# CHECK: S_NOP 0, implicit %0
|
|
name: test0
|
|
isSSA: true
|
|
registers:
|
|
- { id: 0, class: sreg_128 }
|
|
body: |
|
|
bb.0:
|
|
S_NOP 0, implicit-def undef %0.sub0
|
|
S_NOP 0, implicit-def %0.sub1
|
|
S_NOP 0, implicit %0.sub1
|
|
S_NOP 0, implicit-def %0.sub1
|
|
S_NOP 0, implicit %0.sub1
|
|
S_NOP 0, implicit-def %0.sub1
|
|
S_NOP 0, implicit %0
|
|
...
|