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d6a1215edc
This patch corresponds to review: http://reviews.llvm.org/D18592 It allows the PPC back end to generate the xxspltw instruction where we previously only emitted vspltw. llvm-svn: 268516
92 lines
2.8 KiB
LLVM
92 lines
2.8 KiB
LLVM
; RUN: llc -O3 -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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; Test swap removal when a vector splat must be adjusted to make it legal.
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;
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; Test generated from following C code:
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;
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; vector char vc = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
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; vector char vcr;
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; vector short vs = {0, 1, 2, 3, 4, 5, 6, 7};
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; vector short vsr;
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; vector int vi = {0, 1, 2, 3};
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; vector int vir;
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;
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; void cfoo ()
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; {
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; vcr = (vector char){vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5],
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; vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5], vc[5]};
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; }
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;
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; void sfoo ()
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; {
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; vsr = (vector short){vs[6], vs[6], vs[6], vs[6],
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; vs[6], vs[6], vs[6], vs[6]};
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; }
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;
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; void ifoo ()
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; {
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; vir = (vector int){vi[1], vi[1], vi[1], vi[1]};
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; }
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@vc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@vs = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@vi = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@vcr = common global <16 x i8> zeroinitializer, align 16
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@vsr = common global <8 x i16> zeroinitializer, align 16
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@vir = common global <4 x i32> zeroinitializer, align 16
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; Function Attrs: nounwind
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define void @cfoo() {
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entry:
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%0 = load <16 x i8>, <16 x i8>* @vc, align 16
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%vecinit30 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
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store <16 x i8> %vecinit30, <16 x i8>* @vcr, align 16
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ret void
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}
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; Function Attrs: nounwind
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define void @sfoo() {
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entry:
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%0 = load <8 x i16>, <8 x i16>* @vs, align 16
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%vecinit14 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
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store <8 x i16> %vecinit14, <8 x i16>* @vsr, align 16
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ret void
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}
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; Function Attrs: nounwind
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define void @ifoo() {
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entry:
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%0 = load <4 x i32>, <4 x i32>* @vi, align 16
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%vecinit6 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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store <4 x i32> %vecinit6, <4 x i32>* @vir, align 16
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ret void
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}
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; Justification:
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; Byte splat of element 5 (BE) becomes element 15-5 = 10 (LE)
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; which becomes (10+8)%16 = 2 (LE swapped).
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;
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; Halfword splat of element 6 (BE) becomes element 7-6 = 1 (LE)
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; which becomes (1+4)%8 = 5 (LE swapped).
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;
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; Word splat of element 1 (BE) becomes element 3-1 = 2 (LE)
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; which becomes (2+2)%4 = 0 (LE swapped).
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; CHECK-NOT: xxpermdi
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; CHECK-NOT: xxswapd
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; CHECK-LABEL: @cfoo
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; CHECK: lxvd2x
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; CHECK: vspltb {{[0-9]+}}, {{[0-9]+}}, 2
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; CHECK: stxvd2x
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; CHECK-LABEL: @sfoo
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; CHECK: lxvd2x
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; CHECK: vsplth {{[0-9]+}}, {{[0-9]+}}, 5
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; CHECK: stxvd2x
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; CHECK-LABEL: @ifoo
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; CHECK: lxvd2x
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; CHECK: xxspltw {{[0-9]+}}, {{[0-9]+}}, 0
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; CHECK: stxvd2x
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