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The LASTB and LASTA instructions extract the last active element, or element after the last active, from the source vector. The added variants are: Scalar: last(a|b) w0, p0, z0.b last(a|b) w0, p0, z0.h last(a|b) w0, p0, z0.s last(a|b) x0, p0, z0.d SIMD & FP Scalar: last(a|b) b0, p0, z0.b last(a|b) h0, p0, z0.h last(a|b) s0, p0, z0.s last(a|b) d0, p0, z0.d The CLASTB and CLASTA conditionally extract the last or element after the last active element from the source vector. The added variants are: Scalar: clast(a|b) w0, p0, w0, z0.b clast(a|b) w0, p0, w0, z0.h clast(a|b) w0, p0, w0, z0.s clast(a|b) x0, p0, x0, z0.d SIMD & FP Scalar: clast(a|b) b0, p0, b0, z0.b clast(a|b) h0, p0, h0, z0.h clast(a|b) s0, p0, s0, z0.s clast(a|b) d0, p0, d0, z0.d Vector: clast(a|b) z0.b, p0, z0.b, z1.b clast(a|b) z0.h, p0, z0.h, z1.h clast(a|b) z0.s, p0, z0.s, z1.s clast(a|b) z0.d, p0, z0.d, z1.d Please refer to the architecture specification for more details on the semantics of the added instructions. llvm-svn: 336783 |
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.. | ||
AsmParser | ||
Disassembler | ||
InstPrinter | ||
MCTargetDesc | ||
TargetInfo | ||
Utils | ||
AArch64.h | ||
AArch64.td | ||
AArch64A53Fix835769.cpp | ||
AArch64A57FPLoadBalancing.cpp | ||
AArch64AdvSIMDScalarPass.cpp | ||
AArch64AsmPrinter.cpp | ||
AArch64CallingConvention.h | ||
AArch64CallingConvention.td | ||
AArch64CallLowering.cpp | ||
AArch64CallLowering.h | ||
AArch64CleanupLocalDynamicTLSPass.cpp | ||
AArch64CollectLOH.cpp | ||
AArch64CondBrTuning.cpp | ||
AArch64ConditionalCompares.cpp | ||
AArch64ConditionOptimizer.cpp | ||
AArch64DeadRegisterDefinitionsPass.cpp | ||
AArch64ExpandPseudoInsts.cpp | ||
AArch64FalkorHWPFFix.cpp | ||
AArch64FastISel.cpp | ||
AArch64FrameLowering.cpp | ||
AArch64FrameLowering.h | ||
AArch64GenRegisterBankInfo.def | ||
AArch64InstrAtomics.td | ||
AArch64InstrFormats.td | ||
AArch64InstrInfo.cpp | ||
AArch64InstrInfo.h | ||
AArch64InstrInfo.td | ||
AArch64InstructionSelector.cpp | ||
AArch64ISelDAGToDAG.cpp | ||
AArch64ISelLowering.cpp | ||
AArch64ISelLowering.h | ||
AArch64LegalizerInfo.cpp | ||
AArch64LegalizerInfo.h | ||
AArch64LoadStoreOptimizer.cpp | ||
AArch64MachineFunctionInfo.h | ||
AArch64MacroFusion.cpp | ||
AArch64MacroFusion.h | ||
AArch64MCInstLower.cpp | ||
AArch64MCInstLower.h | ||
AArch64PBQPRegAlloc.cpp | ||
AArch64PBQPRegAlloc.h | ||
AArch64PerfectShuffle.h | ||
AArch64PromoteConstant.cpp | ||
AArch64RedundantCopyElimination.cpp | ||
AArch64RegisterBankInfo.cpp | ||
AArch64RegisterBankInfo.h | ||
AArch64RegisterBanks.td | ||
AArch64RegisterInfo.cpp | ||
AArch64RegisterInfo.h | ||
AArch64RegisterInfo.td | ||
AArch64SchedA53.td | ||
AArch64SchedA57.td | ||
AArch64SchedA57WriteRes.td | ||
AArch64SchedCyclone.td | ||
AArch64SchedExynosM1.td | ||
AArch64SchedExynosM3.td | ||
AArch64SchedFalkor.td | ||
AArch64SchedFalkorDetails.td | ||
AArch64SchedKryo.td | ||
AArch64SchedKryoDetails.td | ||
AArch64SchedThunderX2T99.td | ||
AArch64SchedThunderX.td | ||
AArch64Schedule.td | ||
AArch64SelectionDAGInfo.cpp | ||
AArch64SelectionDAGInfo.h | ||
AArch64SIMDInstrOpt.cpp | ||
AArch64StorePairSuppress.cpp | ||
AArch64Subtarget.cpp | ||
AArch64Subtarget.h | ||
AArch64SVEInstrInfo.td | ||
AArch64SystemOperands.td | ||
AArch64TargetMachine.cpp | ||
AArch64TargetMachine.h | ||
AArch64TargetObjectFile.cpp | ||
AArch64TargetObjectFile.h | ||
AArch64TargetTransformInfo.cpp | ||
AArch64TargetTransformInfo.h | ||
CMakeLists.txt | ||
LLVMBuild.txt | ||
SVEInstrFormats.td |