Diego Caballero ef55ff578f [VPlan][LV] Introduce condition bit in VPBlockBase ... This patch introduces a VPValue in VPBlockBase to represent the condition bit that is used as successor selector when a block has multiple successors. This information wasn't necessary until now, when we are about to introduce outer loop vectorization support in VPlan code gen. Reviewers: fhahn, rengolin, mkuper, hfinkel, mssimpso Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D48814 llvm-svn: 336554		2018-07-09 15:57:09 +00:00
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ADT	[OpenEmbedded] Add OpenEmbedded vendor	2018-07-05 23:41:17 +00:00
Analysis	[PhiValues] Adjust unit test to invalidate instructions before deleting them	2018-06-28 15:17:07 +00:00
AsmParser
BinaryFormat
Bitcode
CodeGen
DebugInfo	Move some code from PDBFileBuilder to MSFBuilder.	2018-06-27 21:18:15 +00:00
Demangle
ExecutionEngine	[ORC] Add a symbolAliases function to the Core APIs.	2018-06-26 01:22:29 +00:00
FuzzMutate
IR	Test commit	2018-07-07 16:22:22 +00:00
LineEditor
Linker
MC	[WebAssembly] Fixed disassembler unit test failure.	2018-06-19 00:02:34 +00:00
MI
Object
ObjectYAML
Option
Passes
ProfileData	[NFC] Change sample profile format enum name SPF_Raw_Binary to SPF_Binary.	2018-06-12 05:53:49 +00:00
Support	[Support] Allow JSON serialization of Optional<T> for supported T.	2018-07-09 12:26:09 +00:00
Target	[WebAssembly] Add WebAssemblyException information analysis	2018-06-25 01:20:21 +00:00
tools	[llvm-exegesis] Adjust AArch64 unit test	2018-07-03 10:52:20 +00:00
Transforms	[VPlan][LV] Introduce condition bit in VPBlockBase	2018-07-09 15:57:09 +00:00
XRay
CMakeLists.txt